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1. general description the isp1705 is a utmi+ low pin interface (ulpi) hi-speed universal serial bus (usb) transceiver that is fully compliant with universal serial bus speci?cation rev. 2.0 , on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 and utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . the isp1705 can transmit and receive usb data at high speed (480 mbit/s), full speed (12 mbit/s) and low speed (1.5 mbit/s), and provides a pin-optimized, physical layer front-end attachment to the usb host, peripheral or otg controller with single data rate (sdr) or dual data rate (ddr) ulpi link. the isp1705 can transparently transmit and receive uart signaling. it is ideal for use in portable electronic devices, such as mobile phones, digital still cameras, digital video cameras, personal digital assistants (pdas) and digital audio players. it allows usb application-speci?c integrated circuits (asics), programmable logic devices (plds) or any system chip set to interface with the physical layer of the usb through an 8-pin (ddr) or 12-pin (sdr) interface. the isp1705 can interface to devices with digital i/o voltages in the range of 3.0 v to 3.6 v. the isp1705 is available in hvqfn36 and tfbga36 packages. 2. features n fully complies with: u usb: universal serial bus speci?cation rev. 2.0 u otg: on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 u ulpi: utmi+ low pin interface (ulpi) speci?cation rev. 1.1 n interfaces to usb host, peripheral or otg cores; optimized for portable devices or system asics with built-in ulpi link n complete hi-speed usb physical front-end solution that supports high speed (480 mbit/s), full speed (12 mbit/s) and low speed (1.5 mbit/s) u integrated 45 w 10 % high-speed termination resistors, 1.5 k w 5 % full-speed device pull-up resistor, and 15 k w 5 % host termination resistors u integrated parallel-to-serial and serial-to-parallel converters to transmit and receive u usb clock and data recovery to receive usb data up to 500 ppm u insertion of stuff bits during transmit and discarding of stuff bits during receive u non-return-to-zero inverted (nrzi) encoding and decoding u supports bus reset, suspend, resume and high-speed detection handshake (chirp) isp1705 ulpi hi-speed usb transceiver rev. 01 13 june 2008 product data sheet
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 2 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver n complete usb otg physical front-end that supports host negotiation protocol (hnp) and session request protocol (srp) u supports external charge pump or external v bus power switch u complete control over usb termination resistors u data line and v bus pulsing session request methods u integrated v bus voltage comparators u integrated cable (id) detector n flexible system integration and very low power consumption, optimized for portable devices u 3.0 v to 4.5 v supply voltage input range u internal voltage regulator supplies 2.7 v or 3.3 v and 1.8 v u supports interfacing i/o voltage of 3.0 v to 3.6 v; separate i/o voltage supply pins minimize crosstalk u power down internal regulators in power-down mode when v cc(i/o) is not present or when the chip is not selected u typical operating current of 13 ma to 32 ma, depending on the usb speed and bus utilization u typical current consumption i cc is 70 m a in suspend mode and 0.5 m a in power-down mode u 3-state ulpi interface by the chip_sel or chip_sel_n pin, allowing bus reuse by other applications n highly optimized ulpi compliant u 60 mhz, 8-pin or 12-pin interface between the core and the transceiver, including a 4-bit ddr bus or an 8-bit sdr bus u ddr or sdr interface selectable by pin u supports 60 mhz output clock con?guration u integrated phase-locked loop (pll) supporting input clock frequencies of 13 mhz, 19.2 mhz, 24 mhz or 26 mhz u crystal or clock frequency selectable by pin u fully programmable ulpi-compliant register set u 3-pin or 6-pin full-speed or low-speed serial mode u internal power-on reset (por) circuit n uart interface: u supports transparent uart signaling on dp and dm pins for the uart accessory application u 2.7 v uart signaling on dp and dm pins u entering uart mode by register setting u exiting uart mode by asserting stp or by toggling the chip_sel or chip_sel_n pin n full industrial grade operating temperature range from - 40 c to +85 c n esd compliance: u jesd22-a114d 2 kv contact human body model (hbm) u jesd22-a115-a 200 v machine model (mm) u jesd22-c101-c 500 v charged device model (cdm) u iec 61000-4-2 8 kv contact on the dp and dm pins
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 3 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver n available in small hvqfn36 and tfbga36 restriction of hazardous substances (rohs) compliant, halogen-free and lead-free packages 3. applications n digital still camera n digital tv n digital video disc (dvd) recorder n external storage device, for example: u magneto-optical (mo) drive u optical drive (cd-rom, cd-rw, cd-dvd) u zip drive n mobile phone n mp3 player n pda n printer n scanner n set-top box (stb) n video camera 4. ordering information 5. marking [1] the package marking is the ?rst line of text on the ic package and can be used for ic identi?cation. table 1. ordering information type number package name description version isp1705hn hvqfn36 plastic thermal enhanced very thin quad ?at package; no leads; 36 terminals; body 5 5 0.85 mm sot818-1 ISP1705AET tfbga36 plastic thin ?ne-pitch ball grid array package; 36 balls; body 3.5 3.5 0.8 mm sot912-1 table 2. marking codes type number marking code [1] isp1705hn 1705 ISP1705AET 705a
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 4 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 6. block diagram this ?gure shows the hvqfn pinout. for the tfbga ballout, see t ab le 3 . fig 1. block diagram register map ulpi interface controller usb data serializer usb data deserializer hi-speed usb atx dm dp stp dir nxt data [7:0] 8 004aaa994 clock termination resistors pll crystal oscillator voltage regulator band gap reference voltage rref internal power v cc reg1v8 reg3v3 global clocks xtal2 xtal1 v cc(i/o) interface voltage v bus isp1705 ulpi interface v ref uart buffer data0 clock frequency selection id detector srp charge and discharge resistors otg module v bus comparators port power control fault psw_n cfg1 power-on reset por gnd id 4 5 6 10 9 13 8 14 12 16 17 31 18 19 22 23 1, 2, 24, 25, 27, 28, 30, 36 3, 21, 26, 33 29 n.c. 11 reset_n 20 15 cfg2 32 chip_sel_n 34 chip_sel 35 ddr or sdr selection cfg0 7 data1
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 5 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 7. pinning information 7.1 pinning fig 2. pin con?guration hvqfn36 fig 3. pin con?guration tfbga36 004aaa995 isp1705hn transparent top view dir v cc id reset_n cfg0 v cc(i/o) dp stp dm nxt rref data7 v cc(i/o) data6 data0 v cc(i/o) data5 data1 fault n.c. reg3v3 v bus psw_n gnd xtal1 xtal2 reg1v8 data2 chip_sel chip_sel_n v cc(i/o) cfg2 cfg1 data3 clock data4 9 19 8 20 7 21 6 22 5 23 4 24 3 25 2 26 1 27 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 terminal 1 index area 004aab094 ISP1705AET transparent top view f e d c a b 246 135 ball a1 index area
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 6 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 7.2 pin description table 3. pin description symbol [1] pin type [2] description [3] hvqfn36 (isp1705hn) tfbga36 (ISP1705AET) data1 1 a1 i/o ulpi data pin 1 3-state output; plain input data0 2 b1 i/o ulpi data pin 0 3-state output; plain input v cc(i/o) 3 b2 p input i/o supply voltage; 3.0 v to 3.6 v; a 0.1 m f decoupling capacitor is recommended rref 4 c2 ai/o resistor reference; connect through a 12 k w 1 % resistor to gnd dm 5 c1 ai/o connect to the d - pin of the usb connector ? usb mode: d - input or output ? uart mode: txd output dp 6 d1 ai/o connect to the d+ pin of the usb connector ? usb mode: d+ input or output ? uart mode: rxd input during uart mode, an internal 125 k w 20 % pull-up resistor is present on this pin. cfg0 7 e1 i select sdr or ddr ulpi interface: ? sdr: connect this pin to gnd ? ddr: connect this pin to reg3v3 plain input; ttl v cc 8 f3 p input supply voltage or battery source; 3.0 v to 4.5 v remark: below 3.0 v, usb full-speed and low-speed transactions are not guaranteed to work, though some devices may work with the isp1705 at these voltages. id 9 d3 i identi?cation (id) pin of the micro-usb connector; if this pin is not in use, connect it directly to the reg3v3 pin (an internal 400 k w pull-up resistor is present on this pin) plain input; ttl fault 10 e2 i input for the v bus digital overcurrent or fault detector signal; if this pin is not in use, connect it to gnd plain input, 5 v tolerant n.c. 11 f1, f2 - not connected reg3v3 12 e3 p 3.3 v regulator output for usb mode or 2.7 v regulator output for uart mode; requires parallel 0.1 m f and 4.7 m f capacitors; internally powers atx and other analog circuits; must not be used to power external circuits v bus 13 f4 ai/o connect to the v bus pin of the usb connector; if this pin is not in use, leave it open (r i(idle)(vbus) is present on this pin) psw_n 14 d4 od active-low external v bus power switch or external charge pump enable open-drain output, 4 ma current sinking capability, 5 v tolerant gnd 15 c5, d2, e4 - ground
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 7 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver xtal1 16 f5 ai/o crystal oscillator or clock input; 1.8 v peak input allowed; frequency depends on status on the cfg1 pin xtal2 17 f6 ai/o crystal oscillator output; when a crystal oscillator is used, leave this pin open reg1v8 18 e6 p 1.8 v regulator output; requires parallel 0.1 m f and 4.7 m f capacitors; internally powers the digital core; must not be used to power external circuits dir 19 e5 o ulpi direction signal 3-state output reset_n 20 c4 i active-low, asynchronous reset input plain input v cc(i/o) 21 b5 p input i/o supply voltage; 3.0 v to 3.6 v; a 0.1 m f decoupling capacitor is recommended stp 22 d6 i ulpi stop signal plain input nxt 23 d5 o ulpi next signal 3-state output data7 24 c6 i/o ulpi data pin 7 3-state output; plain input data6 25 b6 i/o ulpi data pin 6 3-state output; plain input v cc(i/o) 26 - p input i/o supply voltage; 3.0 v to 3.6 v; a 0.1 m f decoupling capacitor is recommended data5 27 a6 i/o ulpi data pin 5 3-state output; plain input data4 28 a5 i/o ulpi data pin 4 3-state output; plain input clock 29 a4 o 60 mhz clock output when crystal is attached or clock is applied on the xtal1 pin 3-state output data3 30 a3 i/o ulpi data pin 3 3-state output; plain input cfg1 31 b4 i select crystal or clock frequency with cfg2; see t ab le 6 plain input cfg2 32 b3 i select crystal or clock frequency with cfg1; see t ab le 6 plain input v cc(i/o) 33 - p input i/o supply voltage; 3.0 v to 3.6 v; a 0.1 m f decoupling capacitor is recommended chip_sel_n 34 c3 i active-low chip select input; when this pin is not in use, connect it to gnd plain input table 3. pin description continued symbol [1] pin type [2] description [3] hvqfn36 (isp1705hn) tfbga36 (ISP1705AET)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 8 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] symbol names ending with underscore n (for example, name_n) indicate active-low signals. [2] i = input; o = output; i/o = digital input/output; od = open-drain output; ai/o = analog input/output; p = power supply or ground pin. [3] a detailed description of these pins can be found in section 8.12 . chip_sel 35 - i active-high chip select input; when this pin is not in use, connect it to v cc(i/o) plain input data2 36 a2 i/o ulpi data pin 2 3-state output; plain input gnd exposed die pad - p ground table 3. pin description continued symbol [1] pin type [2] description [3] hvqfn36 (isp1705hn) tfbga36 (ISP1705AET)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 9 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8. functional description 8.1 ulpi interface controller the isp1705 provides a 12-pin interface that is compliant with utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . this interface must be connected to a usb link. the ulpi interface controller provides the following functions: ? ulpi-compliant interface and register set ? allows full control over the usb peripheral or host functionality ? parses the usb transmit and receive data ? prioritizes the usb receive data, usb transmit data, interrupts and register operations ? low-power mode ? transparent uart mode ? 3-pin serial mode ? 6-pin serial mode ? generates rxcmds (status updates) ? maskable interrupts for more information on the ulpi protocol, see section 10 . 8.2 usb serializer and deserializer the usb data serializer prepares data to transmit on the usb bus. to transmit data, the usb link sends a transmit command and data on the ulpi bus. the serializer performs parallel-to-serial conversion, bit stuf?ng and nrzi encoding. for packets with a pid, the serializer adds a sync pattern to the start of the packet, and an eop pattern to the end of the packet. when the serializer is busy and cannot accept any more data, the ulpi interface controller deasserts nxt. the usb data deserializer decodes data received from the usb bus. when data is received, the deserializer strips the sync and eop patterns, and then performs serial-to-parallel conversion, nrzi decoding and discarding of stuff bits on the data payload. the ulpi interface controller sends data to the usb link by asserting dir, and then asserting nxt whenever a byte is ready. the deserializer also detects various receive errors, including bit stuff errors, elasticity buffer underrun or overrun, and byte-alignment errors. 8.3 hi-speed usb (usb 2.0) atx the hi-speed usb atx block is an analog front-end containing the circuitry needed to transmit, receive and terminate the usb bus in high speed, full speed and low speed, for usb peripheral, host or otg implementations. the following circuitry is included: ? differential drivers to transmit data at high speed, full speed and low speed ? differential and single-ended receivers to receive data at high speed, full speed and low speed ? squelch circuit to detect high-speed bus activity
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 10 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver ? high-speed disconnect detector ? 45 w high-speed bus terminations on pins dp and dm ? 1.5 k w pull-up resistor on pin dp ? 15 k w bus terminations on pins dp and dm for details on controlling resistor settings, see t ab le 15 . 8.4 voltage regulator the isp1705 contains a built-in voltage regulator that conditions the v cc supply for use inside the isp1705. the voltage regulator: ? supports input supply range 3. 0v isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 11 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.7 otg module this module contains several sub-blocks that provide all the functionality required by the usb otg speci?cation. speci?cally, it provides the following circuits: ? the id detector to sense the id pin of the micro-usb cable. the id pin dictates which device is initially con?gured as a host and which as a peripheral. ? v bus comparators to determine the v bus voltage level. this is required for the v bus detection, srp and hnp. ? resistors to temporarily charge and discharge v bus . this is required for srp. 8.7.1 id detector the id detector detects which end of the micro-usb cable is plugged in. the id detector must ?rst be enabled by setting the id_pullup register bit to logic 1. if the isp1705 senses a state of the id pin that is different from the previously reported state, an rxcmd status update will be sent to the usb link, or an interrupt will be asserted. ? if the micro-b end of the cable is plugged in (or nothing is plugged in), the isp1705 will report that id_gnd is logic 1. the usb link must be in the b-device state. ? if the micro-a end of the cable is plugged in, the isp1705 will report that id_gnd is logic 0. the usb link must be in the a-device state. the id pin has a weak pull-up resistor (r weakpu(id) ) permanently enabled to avoid the ?oating condition. 8.7.2 v bus comparators the isp1705 provides three comparators to detect the v bus voltage level. the comparators are explained in the following subsections. 8.7.2.1 v bus valid comparator this comparator is used by hosts and a-devices to determine whether the voltage on v bus is at a valid level for operation. the isp1705 minimum threshold for the v bus valid comparator is 4.4 v. any voltage on v bus below this threshold is considered invalid. during power-up, it is expected that the comparator output will be ignored. 8.7.2.2 session valid comparator the session valid comparator is a ttl-level input that determines when v bus is high enough for a session to start. peripherals, a-devices and b-devices use this comparator to detect when a session is started. the a-device also uses this comparator to determine when a session is completed. the session valid threshold of the isp1705 is between 0.8 v to 2.0 v. 8.7.2.3 session end comparator the session end comparator determines when v bus is below the b-device session end threshold of 0.2 v to 0.8 v. the b-device uses this threshold to determine when a session has ended.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 12 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.7.3 srp charge and discharge resistors the isp1705 provides on-chip resistors for short-term charging and discharging of v bus . these are used by the b-device to request a session, prompting the a-device to restore the v bus voltage. first, the b-device makes sure that v bus is fully discharged from the previous session by setting the dischrg_vbus register bit to logic 1 and waiting for sess_end to be logic 1. then the b-device charges v bus by setting the chrg_vbus register bit to logic 1. the a-device sees that v bus is charged above the session valid threshold and starts a session by turning on the v bus voltage. 8.8 port power control for an otg or host application, the isp1705 uses the psw_n pin to control the external power switch for the v bus 5 v supply. the overcurrent detector output of the external power switch can be connected to the fault pin of the isp1705 to indicate to the ulpi link the v bus overcurrent status. for the connection scheme, see figure 4 . when the fault pin is not used, connect it to gnd. 8.9 band gap reference voltage the band gap circuit provides a stable internal voltage reference to bias the analog circuitry. this band gap circuit requires an accurate external reference resistor. connect a 12 k w 1 % resistor between the rref pin and gnd. 8.10 power-on reset (por) an internal por pulse is generated when reg1v8 rises above v por(trip) . the internal por pulse will be generated whenever reg1v8 drops below v por(trip) for more than t w(reg1v8_l) . to give a better view of the functionality, figure 5 shows a possible curve of reg1v8. the internal por starts with logic 0 at t0. at t1, the detector will see the passing of the trip level so that a por pulse is generated to reset all internal circuits. if reg1v8 dips from t2 to t3 for greater than t w(reg1v8_l) , another por pulse is generated. if the dip from t4 to t5 is less than t w(reg1v8_l) , the internal por pulse will not be generated and will remain low. fig 4. digital overcurrent detection scheme 001aai189 isp1705 v bus psw_n fault power switch with fault indicator v bus +5 v
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 13 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.11 power-up, reset and bus idle sequence figure 6 shows a typical start-up sequence. on power-up, the isp1705 performs an internal power-on reset and asserts dir to indicate to the link that the ulpi bus cannot be used. when the internal pll is stable, the isp1705 deasserts dir and drives a 60 mhz clock on the clock pin. the power-up time depends on the v cc supply rise time, the crystal start-up time, and the pll start-up time t startup(pll) . when dir is deasserted, the link must drive the data bus to a valid level. by default, the link must drive data to low. before beginning usb packets, the link must set the reset bit in the func_ctrl register (see section 11.5 ) to reset the isp1705. after the reset bit is set, the isp1705 will assert dir until the internal reset completes. the isp1705 will automatically deassert dir and clear the reset bit when the reset has completed. after every reset, an rxcmd is sent to the link to update usb status information. after this sequence, the ulpi bus is ready for use and the link can start usb operations. if chip select is non-active, the isp1705 will be kept in power-down mode. in power-down mode, all ulpi interface pins will be put in 3-state, the internal regulator will be shut down, and the total current consumption in power-down mode will be less than that in low-power mode. the link can do a hardware reset to the isp1705 by toggling chip select. the recommended sequence is: 1. de-activate chip select. 2. wait for at least t pwrdn . 3. activate chip select. if the low-power mode is entered when v cc(i/o) is lost, see t ab le 9 . the recommended power-up sequence for the link is: 1. apply the v cc and v cc(i/o) voltage. 2. activate chip select. 3. the link waits for at least t pwrup , ignoring all the ulpi pin statuses. 4. the link may start to detect the dir status level. if dir is detected low, the link may send a reset command. the ulpi interface is ready for use. fig 5. internal power-on reset timing 004aab023 reg1v8 t0 t1 t2 t3 t4 t5 v por(trip) por
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 14 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver t1 = v cc is applied to the isp1705. t2 = v cc(i/o) is turned on. ulpi interface pins clock, data[7:0], dir and nxt are in 3-state as long as chip select is non-active. t3 = chip select turns from non-active to active. the isp1705 regulator starts to turn on. ulpi pads are not in 3-state and may drive to either low or high. it is recommended that the link ignores ulpi pins status during t pwrup . t4 = power-on reset threshold is reached and the por pulse is generated. after the por pulse, ulpi pins are driven to a de?ned level. dir is driven to high and the other pins are driven to low. t5 = the pll is stabilized after t d(det)clk(osc) +t startup(pll) . the clock pin starts to output 60 mhz. the dir pin will transition from high to low. the link must drive data[7:0] and stp to low as the idle state. the link will then issue a reset command to initialize the isp1705. t6 = the power-up sequence is completed and the ulpi bus interface is ready for use. fig 6. power-up and reset sequence required before the ulpi bus is ready for use chip_sel_n clock (output) txcmd dir data[7:0] stp nxt 004aaa987 reset command internal clocks stable internal reset rxcmd update bus idle d v cc v cc(i/o) reg1v8 internal por xtal1 t1 t2 t3 t4 t5 t6 t pwrup t d(det)clk(osc) + t startup(pll)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 15 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.11.1 interface protection by default, the isp1705 enables a weak pull-up resistor on stp. if the stp pin is unexpectedly high at any time, the isp1705 will protect the ulpi interface by enabling weak pull-down resistors on data[7:0]. the interface protect feature prevents unwanted activity of the isp1705 whenever the ulpi interface is not correctly driven by the link. for example, when the link powers up more slowly than the isp1705. the interface protect feature can be disabled by setting the intf_prot_dis bit to logic 1. 8.11.2 interface behavior with respect to reset_n the use of the reset_n pin is optional. when reset_n is asserted (low), all logic in the isp1705 will be reset, including the analog circuitry and ulpi registers. during reset, the link must drive data[7:0] and stp to low; otherwise unde?ned behavior may result. when reset_n is deasserted (high), 60 mhz clock will start. figure 7 shows the ulpi interface behavior when reset_n is asserted (low), and subsequently deasserted (high). the behavior of figure 7 applies only when chip select is asserted. if reset_n is not used, it must be connected to v cc(i/o) . 8.11.3 interface behavior with respect to chip select the use of chip select as a power-down control signal is optional. when chip select is deasserted, the isp1705 will 3-state ulpi pins and power-down the internal circuitry. if chip select is not used as a power-down control signal, chip_sel_n must be connected to low. figure 8 shows the ulpi interface behavior when chip select is asserted and subsequently deasserted. fig 7. interface behavior with respect to reset_n clock 004aab065 stp reset_n data[7:0] dir nxt hi-z (input) hi-z (input) hi-z (input) hi-z (input) hi-z (link must drive) hi-z (link must drive)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 16 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.12 detailed description of pins 8.12.1 data[7:0] bidirectional data bus pins. the usb link must drive data[7:0] to low when the ulpi bus is idle. when the link has data to transmit to the phy, it drives a nonzero value. weak pull-down resistors are incorporated into data[7:0] pins as part of the interface protect feature. for details, see section 8.11.1 . data[7:0] pins can also be 3-stated when chip select is deasserted. these pins can be recon?gured to carry various data types when the chip is not in synchronous mode. for details, see section 9.2 . 8.12.2 v cc(i/o) the input supply power pin that sets the i/o voltage level. a 0.1 m f decoupling capacitor is recommended on each v cc(i/o) pin. v cc(i/o) powers the on-chip pads of the following pins: ? cfg1 ? cfg2 ? chip_sel ? chip_sel_n ? clock ? data[7:0] ? dir ? nxt ? stp ? reset_n fig 8. interface behavior with respect to chip select clock 004aaa988 stp chip_sel_n data[7:0] dir nxt hi-z (input) hi-z (input) hi-z (ignored) hi-z (ignored) hi-z (ignored) t pwrdn hi-z hi-z
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 17 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.12.3 rref resistor reference analog i/o pin. a 12 k w 1 % resistor must be connected between the rref pin and gnd. this provides an accurate voltage reference that biases internal analog circuitry. less accurate resistors cannot be used. it will affect the biasing current for analog circuits, thus the usb signal quality. 8.12.4 dp and dm when the isp1705 is in usb mode, the dp pin functions as the usb data plus line, and the dm pin functions as the usb data minus line. when the isp1705 is in transparent uart mode, the dp pin functions as the uart rxd input pin, and the dm pin functions as the uart txd output pin. the dp and dm pins must be connected to the d+ and d - pins of the usb receptacle. 8.12.5 cfg0 this input pin is used to select the sdr or ddr interface. for the sdr interface, connect this pin to gnd. for the ddr interface, connect this pin to reg3v3. 8.12.6 v cc main input supply voltage for the isp1705. the isp1705 operates correctly when v cc is between 3.0 v and 4.5 v. a 0.1 m f decoupling capacitor is recommended. 8.12.7 id for otg applications, the id (identi?cation) pin is connected to the id pin of the micro-ab receptacle. as de?ned in on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 , the id pin dictates the initial role of the link. if id is detected as high, the link must assume the role of a peripheral. if id is detected as low, the link must assume a host role. roles can be swapped at a later time by using hnp. the isp1705 provides an internal pull-up resistor (r up(id) ) to sense the state of the id pin. the pull-up resistor must ?rst be enabled by setting the id_pullup register bit to logic 1. if the state of id has changed, the isp1705 will send an rxcmd or interrupt to the link. if the link does not receive any rxcmd or interrupt by time t id , then the id state has not changed. the isp1705 also provides an internal weak pull-up resistor (r weakpu(id) ). this weak pull-up resistor is always enabled to avoid a possible ?oating condition on the id pin. 8.12.8 fault this pin is used to detect the v bus fault condition. if the function is not used, this pin must be connected to ground to avoid ?oating input. if an external v bus overcurrent or fault detection circuit is used, the output fault indicator of that circuit can be connected to the fault input pin. the use_ext_vbus_ind bit in the otg_ctrl register (see section 11.7 ) and the ind_passthru bit in the intf_ctrl register (see section 11.6 ) must be set to logic 1. the isp1705 will inform the link of v bus fault events by sending rxcmds on the ulpi bus. the fault input pin is mapped to the a_vbus_vld bit in rxcmd. any changes to the fault input will trigger rxcmd carrying the fault condition with a_vbus_vld.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 18 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver for details, see section 10.3.2 and section 10.3.3 . 8.12.9 reg3v3 and reg1v8 these are output voltage pins from the internal regulator. these supplies are used internally to power digital and analog circuits. for proper operation of the regulator, pins reg3v3 and reg1v8 must each be connected to a 0.1 m f capacitor in parallel with a 4.7 m f low esr capacitor. reg3v3 powers on-chip pads of the following pins: ? cfg0 ? dm ? dp ? fault ? id ? psw_n ? rref 8.12.10 v bus this i/o pin acts as an input to v bus comparators, and also as a power supply pin for srp charge and discharge resistors. for details, see figure 9 . the v bus pin requires a capacitive load. t ab le 4 provides the recommended capacitor values for various applications. table 4. recommended v bus capacitor value application v bus capacitor (c vbus ) otg 1 m f to 6.5 m f, 10 v standard host 120 m f 20 %, 10 v standard peripheral 1 m f to 10 m f, 10 v
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 19 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 8.12.11 psw_n the psw_n pin is an active-low open-drain output pin. it is used to control external charge pumps or v bus power switches to supply v bus . when in use, an external pull-up resistor is required. this allows for per-port or ganged power control. to enable the external power source by driving psw_n to low, the link must set the drv_vbus_ext bit in the otg_ctrl register (see section 11.7 ) to logic 1. t ab le 5 summarizes settings to drive 5 v on v bus . 8.12.12 xtal1 and xtal2 xtal1 is the crystal oscillator input, and xtal2 is the crystal oscillator output. the allowed crystal or clock frequency on the xtal1 pin is selectable by the cfg1 and cfg2 pins, as shown in t ab le 6 . when a clock is driven into xtal1, xtal2 must be left open. fig 9. v bus pin internal pull-up and pull-down scheme 004aab045 r up(vbus) r dn(vbus) r i(idle)(vbus) v bus comparators dischrg_ vbus chrg_vbus v bus reg3v3 isp1705 table 5. otg_ctrl register power control bits drv_vbus_ext power source used 0 external 5 v v bus power source disabled (psw_n = high) 1 external 5 v v bus power source enabled (psw_n = low) table 6. allowed crystal or clock frequency on the xtal1 pin pin cfg1 pin cfg2 allowed crystal or clock frequency on the xtal1 pin low low 19.2 mhz low high 26 mhz high low 24 mhz high high 13 mhz
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 20 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver if a crystal is attached, it requires a capacitor on each terminal of the crystal to gnd. the recommended crystal speci?cation and required external capacitors are given in t ab le 7 and t ab le 8 . [1] speci?ed by the crystal manufacturer. [1] speci?ed by the crystal manufacturer. 8.12.13 dir ulpi direction output pin. synchronous to the rising edge of clock. controls the direction of the data bus. by default, the isp1705 holds dir at low, causing the data bus to be an input. when dir is low, the isp1705 listens for data from the link. the isp1705 pulls dir to high only when it has data to send to the link, which is for one of two reasons: ? to send data (usb receive or register reads) and rxcmd status updates to the link. ? to block the link from driving the data bus during power-up, reset and low power (suspend) mode. this pin can be 3-stated when chip select is deasserted. 8.12.14 reset_n an active-low asynchronous reset pin that resets all circuits in the isp1705. the isp1705 contains an internal power-on reset circuit, and therefore using the reset_n pin is optional. if reset_n is not used, it must be connected to v cc(i/o) . for details on using reset_n, see section 8.11.2 . 8.12.15 stp ulpi stop input pin. synchronous to the rising edge of clock. the link must assert stp to signal the end of a usb transmit packet or a register write operation. when dir is asserted, the link can optionally assert stp for one clock cycle to abort the isp1705, causing it to deassert dir in the next clock cycle. 8.12.16 nxt ulpi next data output pin. synchronous to the rising edge of clock. the isp1705 holds nxt at low, by default. when dir is low and the link is sending data to the isp1705, nxt will be asserted to notify the link to provide the next data byte. when dir is high table 7. external capacitor values for 13 mhz or 19.2 mhz clock frequency load capacitance c l of the crystal [1] maximum series resistance r s of the crystal [1] external capacitor c xtal value 10 pf < 180 w 18 pf 20 pf < 100 w 39 pf table 8. external capacitor values for 24 mhz or 26 mhz clock frequency load capacitance c l of the crystal [1] maximum series resistance r s of the crystal [1] external capacitor c xtal value 10 pf < 140 w 18 pf 20 pf < 60 w 39 pf
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 21 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver and the isp1705 is sending data to the link, nxt will be asserted to notify the link that another valid byte is on the bus. nxt is not used for register read data or the rxcmd status update. this pin can be 3-stated when chip select is deasserted. 8.12.17 clock a 60 mhz interface clock to synchronize the ulpi bus. all ulpi pins are synchronous to the rising edge of clock. the isp1705 provides two clocking options: ? a crystal is attached between the xtal1 and xtal2 pins. ? a clock is driven into the xtal1 pin, with the xtal2 pin left unconnected. 8.12.18 cfg1, cfg2 these input pins are used to select the crystal or clock frequency. for details, see t ab le 6 . 8.12.19 chip_sel, chip_sel_n when chip select is deasserted, ulpi pins data[7:0], clock, dir and nxt are 3-stated and the stp input is ignored; internal circuits are powered-down as well. when chip select is asserted, the isp1705 will operate normally. both the chip_sel and chip_sel_n pins must be asserted for the chip select to function. if any of the two is deasserted, the chip will enter power-down mode. 8.12.20 gnd global ground signal. to ensure the correct operation of the isp1705, gnd must be soldered to the cleanest available ground.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 22 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 9. modes of operation 9.1 power modes when both v cc(i/o) and v cc are not powered, there will be no leakage from the v bus pin to all the remaining pins, including v cc and v cc(i/o) . applying v bus within the normal range will not damage the isp1705 chip. when both v cc and v cc(i/o) are powered and are within the operating voltage range, the isp1705 will be fully functional as in normal mode. when v cc(i/o) is powered and the v cc voltage is below the operating range of the isp1705, the application system must detect the low voltage condition and set chip select to deassert (that is, put the isp1705 in power-down mode). this is to protect the ulpi and usb interfaces from driving wrong levels. under this condition, the v cc(i/o) voltage will not leak to usb pins (v bus , dp, dm and id) and the v cc pin. all the digital pins (see section 8.12.2 ) powered by v cc(i/o) are con?gured as high-impedance inputs. these pins must be driven to a de?ned state or terminated by using pull-up or pull-down resistors to avoid a ?oating input condition. other pins (see section 8.12.9 ) are not powered. 9.1.1 normal mode in normal mode, both v cc and v cc(i/o) are powered. chip select is asserted. the isp1705 is fully functional. 9.1.2 power-down mode when v cc(i/o) is not present or when chip select is deasserted, the isp1705 is put into power-down mode. in this mode, internal regulators are powered down to keep the v cc current to a minimum. the voltage on the v cc pin will not leak to the v cc(i/o) and/or v bus pins. in this mode, the isp1705 pin states are given in t ab le 9 . [1] when i/o pins are not powered, the input buffer is disabled and will ignore the external input level. the input pins, however, should not be driven by another voltage source to prevent leakage. [2] these pins must not be externally driven to high. otherwise, the isp1705 behavior is unde?ned and leakage current will occur. when v cc(i/o) is not present, all the digital pins (see section 8.12.2 ) that are powered by v cc(i/o) are not powered. other pins (see section 8.12.9 ) are also not powered. table 9. pin states in power-down mode pin name [1] pin state when v cc(i/o) is not present pin state when v cc(i/o) is present and chip select is not active v cc 3.0 v to 4.5 v 3.0 v to 4.5 v v cc(i/o) not powered [2] 3.0 v to 3.6 v chip_sel, chip_sel_n not powered [2] high cfg1, cfg2, reset_n, clock, stp, nxt, dir, data[7:0] not powered [2] 3.0 v to 3.3 v cfg0, dp, dm, v bus , id, reg1v8, reg3v3, xtal1, xtal2, rref, psw_n, fault not powered [2] not powered [2]
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 23 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver when the isp1705 is put into power-down mode by disabling chip select, all the digital pins (see section 8.12.2 ) that are powered by v cc(i/o) are con?gured as high-impedance inputs. these pins must be driven to de?ned states or terminated by using pull-up or pull-down resistors to avoid a ?oating input condition. other pins (see section 8.12.9 ) are not powered. in this mode, minimum current will be drawn by v cc(i/o) to detect the chip select status. 9.2 ulpi modes the isp1705 ulpi interface can be programmed to operate in ?ve modes. in each mode, the signals on the data bus are recon?gured as described in the following subsections. setting more than one mode will lead to unde?ned behavior. 9.2.1 synchronous mode this is default mode. on power-up, and when clock is stable, the isp1705 will enter synchronous mode. in synchronous mode, the link must synchronize all ulpi signals to clock, meeting the set-up and hold times as de?ned in section 15 . this mode is used by the link to perform the following tasks: ? high-speed detection handshake (chirp) ? transmit and receive usb packets ? read from and write to registers ? receive usb status updates (rxcmds) from the isp1705 for more information on various synchronous mode protocols, see section 10 . table 10. ulpi signal description signal name direction on the isp1705 [1] signal description clock o 60 mhz interface clock : when a crystal is attached or a clock is driven into the xtal1 pin, the isp1705 will drive a 60 mhz output clock. during low-power, serial and uart modes, the clock can be turned off to save power. data[7:0] i/o 8-bit data bus : in synchronous mode, the link drives data[7:0] to low by default. the link initiates transfers by sending a nonzero data pattern called a txcmd (transmit command). in synchronous mode, the direction of data[7:0] is controlled by dir. contents of data[7:0] lines must be ignored for exactly one clock cycle whenever dir changes state. this is called a turnaround cycle. data lines have ?xed directions and different meanings in low-power, 3-pin serial and uart modes.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 24 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] i = input; o = output. 9.2.2 low-power mode when the usb bus is idle, the link can place the isp1705 into low-power mode (also called suspend mode). in low-power mode, the data bus de?nition changes to that shown in t ab le 11 . to enter low-power mode, the link sets the suspendm bit in the func_ctrl register (see section 11.5 ) to logic 0. to exit low-power mode, the link asserts the stp signal. after exiting low-power mode, the isp1705 will send an rxcmd to the link if a change was detected in any interrupt source, and the change still exists. an rxcmd may not be sent if the interrupt condition is removed before exiting. the isp1705 will draw only suspend current from the v cc supply; see t ab le 53 . during low-power mode, the clock on xtal1 may be stopped. the clock must be started again before asserting stp to exit low-power mode. for more information on low-power mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . dir o direction : controls the direction of data bus data[7:0]. in synchronous mode, the isp1705 drives dir to low by default, making the data bus an input so the isp1705 can listen for txcmd from the link. the isp1705 drives dir to high only when it has data for the link. when dir and nxt are high, the byte on the data bus contains decoded usb data. when dir is high and nxt is low, the byte contains status information called an rxcmd (receive command). the only exception to this rule is when the phy returns register read data, where nxt is also low, replacing the usual rxcmd byte. every change in dir causes a turnaround cycle on the data bus, during which data[7:0] is not valid and must be ignored by the link. dir is always asserted during low-power, serial and uart modes. stp i stop : in synchronous mode, the link drives stp to high for one cycle after the last byte of data is sent to the isp1705. the link can optionally assert stp to force dir to be deasserted. in low-power, serial and uart modes, the link holds stp at high to wake up the isp1705, causing the ulpi bus to return to synchronous mode. nxt o next : in synchronous mode, the isp1705 drives nxt to high to throttle data. if dir is low, the isp1705 asserts nxt to notify the link to place the next data byte on data[7:0] in the following clock cycle. if dir is high, the isp1705 asserts nxt to notify the link that a valid usb data byte is on data[7:0] in the current cycle. the isp1705 always drives an rxcmd when dir is high and nxt is low, unless register read data is to be returned to the link in the current cycle. nxt is not used in low-power, serial and uart modes. table 10. ulpi signal description continued signal name direction on the isp1705 [1] signal description table 11. signal mapping during low-power mode signal maps to direction [1] description linestate0 data0 o combinatorial linestate0 directly driven by the analog receiver linestate1 data1 o combinatorial linestate1 directly driven by the analog receiver
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 25 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] i = input; o = output. 9.2.3 6-pin full-speed or low-speed serial mode if the link requires a 6-pin serial interface to transmit and receive full-speed or low-speed usb data, it can set the isp1705 to 6-pin serial mode. in 6-pin serial mode, the data bus de?nition changes to that shown in t ab le 12 . to enter 6-pin serial mode, the link sets the 6pin_fsls_serial bit in the intf_ctrl register (see section 11.6 ) to logic 1. to exit 6-pin serial mode, the link asserts the stp signal. this is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed functionality. an interrupt pin is also provided to inform the link of usb events. if the link requires clock to be running during 6-pin serial mode, the clock_suspendm register bit must be set to logic 1 before entering 6-pin serial mode. for more information on 6-pin serial mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . [1] i = input; o = output. 9.2.4 3-pin full-speed or low-speed serial mode if the link requires a 3-pin serial interface to transmit and receive full-speed or low-speed usb data, it can set the isp1705 to 3-pin serial mode. in 3-pin serial mode, the data bus de?nition changes to that shown in t ab le 13 . to enter 3-pin serial mode, the link sets the 3pin_fsls_serial bit in the intf_ctrl register (see section 11.6 ) to logic 1. to exit 3-pin serial mode, the link asserts the stp signal. this is provided primarily for links that contain legacy full-speed or low-speed functionality, providing a more cost-effective upgrade path to high-speed functionality. an interrupt pin is also provided to inform the link of usb events. if the link requires clock to be running during 3-pin serial mode, the clock_suspendm register bit must be set to logic 1 before entering 3-pin serial mode. reserved data2 o reserved; the isp1705 will drive this pin to low int data3 o active-high interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs reserved data[7:4] o reserved; the isp1705 will drive these pins to low table 11. signal mapping during low-power mode continued signal maps to direction [1] description table 12. signal mapping for 6-pin serial mode signal maps to direction [1] description tx_enable data0 i active-high transmit enable tx_dat data1 i transmit differential data on dp and dm tx_se0 data2 i transmit single-ended zero on dp and dm int data3 o active-high interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs rx_dp data4 o single-ended receive data from dp rx_dm data5 o single-ended receive data from dm rx_rcv data6 o differential receive data from dp and dm reserved data7 o reserved; the isp1705 will drive this pin to low
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 26 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver for more information on 3-pin serial mode enter and exit protocols, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . [1] i = input; o = output. 9.2.5 transparent uart mode in transparent uart mode, the isp1705 functions as a voltage level shifter between following pins: ? from pin data0 (v cc(i/o) level) to pin dm (2.7 v level). ? from pin dp (2.7 v level) to pin data1 (v cc(i/o) level). the usb transceiver is used to drive the uart transmitting signal on the dm line. the rise time and the fall time of the transmitting signal is determined by whether a full-speed or low-speed transceiver is in use. it is recommended to use a low-speed transceiver if the uart bit rate is below 921 kbit/s for better emi performance. if the uart bit rate is equal to or above 921 kbit/s, a full-speed transceiver can be used. in transparent uart mode, data bus de?nitions change to that shown in t ab le 14 . [1] i = input; o = output. transparent uart mode is entered by setting some register bits in ulpi registers. the recommended sequence is: table 13. signal mapping for 3-pin serial mode signal maps to direction [1] description tx_enable data0 i active-high transmit enable dat data1 i/o transmit differential data on dp and dm when tx_enable is high receive differential data from dp and dm when tx_enable is low se0 data2 i/o transmit single-ended zero on dp and dm when tx_enable is high receive single-ended zero from dp and dm when tx_enable is low int data3 o active-high interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs reserved data[7:4] o reserved; the isp1705 will drive these pins to low table 14. uart signal mapping signal maps to direction [1] description txd data0 i uart txd signal that is routed to the dm pin rxd data1 o uart rxd signal that is routed from the dp pin reserved data2 o reserved; the isp1705 will drive this pin to low in uart mode int data3 o active-high interrupt indication; will be asserted and latched whenever any unmasked interrupt occurs reserved data[7:4] o reserved; the isp1705 will drive these pins to low in uart mode
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 27 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 1. set the xcvrselect[1:0] bits in the func_ctrl register (see section 11.5 )to10b (low speed) or 01b (full speed). this setting affects the rise time and the fall time of the uart transmitting signal on the dm line. 2. set the dp_pulldown and dm_pulldown bits in the otg_ctrl register (see section 11.7 ) to logic 0. 3. set the termselect bit in the func_ctrl register (see section 11.5 ) to logic 0 (power-on default value). remark: mandatory when a full-speed driver is used and optional for a low-speed driver. 4. set the txd_en and rxd_en bits in the carkit_ctrl register (see section 11.14 ) to logic 1. these two bits must be set together in one txcmd. 5. set the carkit_mode bit in the intf_ctrl register (see section 11.6 ) to logic 1. remark: the carkit_mode, txd_en and rxd_en bits must be set to logic 1. the sequence of setting these register bits is ignored. after the register con?guration is complete: 1. a weak pull-up resistor will be enabled on the dp and data0 pins. this is to avoid the possible ?oating condition on these input pins when uart mode is enabled. 2. the 39 w serial termination resistors on the dp and dm pins will be enabled. 3. one clock cycle after dir goes from low to high, the isp1705 will drive the data bus for ?ve clock cycles. this is to charge the data0 pin to a high level for a slow link. however, the link can start driving data0 to high immediately after the turnaround cycle. 4. uart buffers between data0 or data1 and dm or dp are enabled. transparent uart mode is entered. remark: the dp pin will be slowly charged up to high by the weak pull-up resistor. the time needed depends on the capacitive loading on dp. by default, the clock is powered down when the isp1705 enters uart mode. if the link requires clock to be running in uart mode, it can set the clock_suspendm bit in the intf_ctrl register (see section 11.6 ) to logic 1 before entering uart mode. transparent uart mode is exited by asserting the stp pin to high or by toggling chip select. the int pin ( data3) is asserted and latched whenever an unmasked interrupt event occurs. when the link detects int as high, it must wake up the phy from transparent uart mode by asserting stp. when the phy is in synchronous mode, the link can read the usb_intr_l register (see section 11.11 ) to determine the source of the interrupt. note that the isp1705 does not implement the optional carkit interrupt registers. an alternative way to exit uart mode is to set chip select to non-active for more than t pwrdn and then set it to active. a power-on reset will be generated and the ulpi bus will be put in default synchronous mode.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 28 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver (1) clock remains powered when the clock_suspendm register bit is set to logic 1. (2) clock is powered down when the clock_suspendm register bit is logic 0 (default). fig 10. interface behavior when entering uart mode (1) clock remains powered when the clock_suspendm register bit is set to logic 1. (2) clock is powered down when the clock_suspendm register bit is logic 0 (default). fig 11. interface behavior when exiting uart mode 004aaa865 clock (2) data[7:0] txcmd (regw) data 0001 0001 dir stp nxt uart mode turnaround uart mode signals clock (1) 004aaa867 dir stp nxt uart mode clock (2) data[7:0] uart mode signals synchronous mode signals turnaround 0000 0000 clock (1)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 29 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 9.3 usb state transitions a hi-speed usb peripheral, host or otg device handles more than one electrical state as de?ned in universal serial bus speci?cation rev. 2.0 and on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 . the isp1705 accommodates various states through register settings of the xcvrselect[1:0], termselect, opmode[1:0], dp_pulldown and dm_pulldown bits. t ab le 15 summarizes operating states. the values of register settings in t ab le 15 will force resistor settings as also given in t ab le 15 . resistor setting signals are de?ned as follows: ? rpu_dp_en enables the 1.5 k w pull-up resistor on dp ? rpd_dp_en enables the 15 k w pull-down resistor on dp ? rpd_dm_en enables the 15 k w pull-down resistor on dm ? hsterm_en enables the 45 w termination resistors on dp and dm it is up to the link to set the desired register settings. table 15. operating states and their corresponding resistor settings signaling mode register settings internal resistor settings xcvr select [1:0] term select opmode [1:0] dp_ pull down dm_ pull down rpu_ dp_en rpd_ dp_en rpd_ dm_en hsterm_ en general settings 3-state drivers xxb xb 01b xb xb 0b 0b 0b 0b power up or v bus isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 30 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver peripheral high speed or full speed suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b peripheral high speed or full speed resume 01b 1b 10b 0b 0b 1b 0b 0b 0b peripheral test j or test k 00b 0b 10b 0b 0b 0b 0b 0b 1b otg settings otg device peripheral chirp 00b 1b 10b 0b 1b 1b 0b 1b 0b otg device peripheral high speed 00b 0b 00b 0b 1b 0b 0b 1b 1b otg device peripheral full speed 01b 1b 00b 0b 1b 1b 0b 1b 0b otg device peripheral high speed and full speed suspend 01b 1b 00b 0b 1b 1b 0b 1b 0b otg device peripheral high speed and full speed resume 01b 1b 10b 0b 1b 1b 0b 1b 0b otg device peripheral test j or test k 00b 0b 10b 0b 1b 0b 0b 1b 1b table 15. operating states and their corresponding resistor settings continued signaling mode register settings internal resistor settings xcvr select [1:0] term select opmode [1:0] dp_ pull down dm_ pull down rpu_ dp_en rpd_ dp_en rpd_ dm_en hsterm_ en
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 31 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10. protocol description 10.1 ulpi references the isp1705 provides a 12-pin ulpi interface to communicate with the link. it is highly recommended that users of the isp1705 read utmi+ speci?cation rev. 1.0 and utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . commands between the isp1705 and the link are described in the following subsections. 10.2 txcmd by default, the link must drive the ulpi bus to its idle state of 00h. to send commands and usb packets, the link drives a nonzero value on data[7:0] to the isp1705 by sending a byte called txcmd. commands include usb packet transmissions, and register reads and writes. once the txcmd is interpreted and accepted by the isp1705, the nxt signal is asserted and the link can follow up with the required number of data bytes. the txcmd byte format is given in t ab le 16 . any values other than those in t ab le 16 are illegal and will result in unde?ned behavior. various txcmd packet and register sequences are given in later sections. 10.3 rxcmd the isp1705 communicates status information to the link by asserting dir and sending an rxcmd byte on the data bus. the rxcmd data byte format follows utmi+ low pin interface (ulpi) speci?cation rev. 1.1 and is given in t ab le 17 . table 16. txcmd byte format command type name command code data[7:6] command payload data[5:0] command name command description idle 00b 00 0000b noop no operation. 00h is the idle value of the data bus. the link must drive noop by default. packet transmit 01b 00 0000b nopid transmit usb data that does not have a pid, such as chirp and resume signaling. the isp1705 starts transmitting only after accepting the next data byte. 00 xxxxb pid transmit usb packet. data[3:0] indicates usb packet identi?er pid[3:0]. register write 10b 10 1111b extw extended register write command (optional). the 8-bit address must be provided after the command is accepted. xx xxxxb regw register write command with 6-bit immediate address. register read 11b 10 1111b extr extended register read command (optional). the 8-bit address must be provided after the command is accepted. xx xxxxb regr register read command with 6-bit immediate address.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 32 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver the isp1705 will automatically send an rxcmd whenever there is a change in any of the rxcmd data ?elds. the link must be able to accept an rxcmd at any time; including single rxcmds, back-to-back rxcmds, and rxcmds at any time during usb receive packets when nxt is low. an example is shown in figure 12 . for details and diagrams, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 10.3.1 linestate encoding linestate[1:0] re?ects the current state of dp and dm. whenever the isp1705 detects a change in dp or dm, an rxcmd will be sent to the link with the new linestate[1:0] value. the value given on linestate[1:0] depends on the setting of various registers. t ab le 18 shows the linestate[1:0] encoding for upstream facing ports, which applies to peripherals. t ab le 19 shows the linestate[1:0] encoding for downstream facing ports, which applies to host controllers. dual-role devices must choose the correct table, depending on whether it is in peripheral or host mode. table 17. rxcmd byte format data name description and value 1 to 0 linestate linestate signals : for a de?nition of linestate, see section 10.3.1 . data0 linestate0 data1 linestate1 3to2 v bus state encoded v bus voltage state : for an explanation of the v bus state, see section 10.3.2 . 5 to 4 rxevent encoded usb event signals : for an explanation of rxevent, see section 10.3.4 . 6 id re?ects the state of the id pin. valid 50 ms after id_pullup is set to logic 1. 7 alt_int by default, this signal is not used and is not needed in typical designs. optionally, the link can enable the bvalid_rise and/or bvalid_fall bits in the pwr_ctrl register (see section 11.15 ). corresponding changes in bvalid will cause an rxcmd to be sent to the link with the alt_int bit asserted. fig 12. single and back-to-back rxcmds from the isp1705 to the link clock rxcmd data [ 7:0 ] rxcmd rxcmd 004aaa695 dir stp nxt single rxcmd back-to-back rxcmds turnaround turnaround turnaround turnaround
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 33 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] !squelch indicates inactive squelch. !hs_differential_receiver_output indicates inactive hs_differential_receiver_output. [1] !squelch indicates inactive squelch. !hs_differential_receiver_output indicates inactive hs_differential_receiver_output. 10.3.2 v bus state encoding usb devices must monitor the v bus voltage for purposes such as overcurrent detection, starting a session and srp. the v bus state ?eld in the rxcmd is an encoding of the voltage level on v bus . the sess_end and sess_vld indicators in the v bus state are directly taken from the internal comparators built-in to the isp1705, and encoded as shown in t ab le 17 and t ab le 20 . table 18. linestate[1:0] encoding for upstream facing ports: peripheral dp_pulldown = 0. [1] mode value full speed high speed chirp xcvrselect[1:0] 01, 11 00 00 termselect 1 0 1 linestate[1:0] 00 se0 squelch squelch 01 fs-j !squelch !squelch and hs_differential_receiver_output 10 fs-k invalid !squelch and !hs_differential_receiver_output 11 se1 invalid invalid table 19. linestate[1:0] encoding for downstream facing ports: host dp_pulldown and dm_pulldown = 1. [1] mode value low speed full speed high speed chirp xcvrselect[1:0] 10 01, 11 00 00 termselect 1 1 0 0 opmode[1:0] x x 00, 01 or 11 10 linestate[1:0] 00 se0 se0 squelch squelch 01 ls-k fs-j !squelch !squelch and hs_differential_receiver_output 10 ls-j fs-k invalid !squelch and !hs_differential_receiver_output 11 se1 se1 invalid invalid table 20. encoded v bus voltage state value v bus voltage sess_end sess_vld a_vbus_vld 00 v bus isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 34 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver the a_vbus_vld indicator in the v bus state provides several options and must be con?gured based on current draw requirements. a_vbus_vld can input from one or more v bus voltage indicators, as shown in figure 13 . a description on how to use and select the v bus state encoding is given in section 10.3.3 . 10.3.3 using and selecting the v bus state encoding the v bus state encoding is shown in t ab le 20 . the isp1705 will send an rxcmd to the link whenever there is a change in the v bus state. to receive v bus state updates, the link must ?rst enable the corresponding interrupts in the usb_intr_en_r and usb_intr_en_f registers. the link can use the v bus state to monitor v bus and take appropriate actions. t ab le 21 shows the recommended usage for typical applications. 10.3.3.1 standard usb host controllers for standard hosts, the system must be able to provide 500 ma on v bus in the range of 4.75 v to 5.25 v. an external circuit must be used to detect overcurrent conditions. if the external overcurrent detector provides a digital fault signal, then the fault signal must be connected to the isp1705 fault input pin, and the link must do the following: 1. set the ind_compl bit in the intf_ctrl register (see section 11.6 ) to logic 0 or logic 1, depending on the polarity of the external fault signal. 2. set the use_ext_vbus_ind bit in the otg_ctrl register (see section 11.7 ) to logic 1. fig 13. rxcmd a_vbus_vld indicator source 004aaa698 v bus (0, x) (1, 0) fault ind_compl (1, 1) use_ext_vbus_ind, ind_passthru rxcmd a_vbus_vld a_vbus_vld comparator internal a_vbus_vld complement output fault indicator table 21. v bus indicators in rxcmd required for typical applications application a_vbus_vld sess_vld sess_end standard host yes no no standard peripheral no yes no otg a-device yes yes no otg b-device no yes yes
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 35 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 3. if it is not necessary to qualify the fault indicator with the internal a_vbus_vld comparator, set the ind_passthru bit in the intf_ctrl register (see section 11.6 ) to logic 1. 10.3.3.2 standard usb peripheral controllers standard peripherals must be able to detect when v bus is at a suf?cient level for operation. sess_vld must be enabled to detect the start and end of usb peripheral operations. detection of a_vbus_vld and sess_end thresholds is not needed for standard peripherals. 10.3.3.3 otg devices when an otg device is con?gured as an otg a-device, it must be able to provide a minimum of 8 ma on v bus . if the otg a-device provides less than 100 ma, then there is no need for an overcurrent detection circuit because the internal a_vbus_vld comparator is suf?cient. if the otg a-device provides more than 100 ma on v bus , an overcurrent detector must be used and section 10.3.3.1 applies. the otg a-device also uses sess_vld to detect when an otg b-device is initiating v bus pulsing srp. when an otg device is con?gured as an otg b-device, sess_vld must be used to detect when v bus is at a suf?cient level for operation. sess_end must be used to detect when v bus has dropped to a low level, allowing the b-device to safely initiate v bus pulsing srp. 10.3.4 rxevent encoding the rxevent ?eld (see t ab le 22 ) of the rxcmd informs the link of information related packets received on the usb bus. rxactive and rxerror are de?ned in usb 2.0 transceiver macrocell interface (utmi) speci?cation ver. 1.05 . hostdisconnect is de?ned in utmi+ speci?cation rev. 1.0 . a short de?nition is also given in the following subsections. 10.3.4.1 rxactive when the isp1705 has detected a sync pattern on the usb bus, it signals an rxactive event to the link. an rxactive event can be communicated using two methods. the ?rst method is for the isp1705 to simultaneously assert dir and nxt. the second method is for the isp1705 to send an rxcmd to the link with the rxactive ?eld in the rxevent bits set to logic 1. the link must be capable of detecting both methods. rxactive frames the receive packet from the ?rst byte to the last byte. the link must assume that rxactive is set to logic 0 when indicated in an rxcmd or when dir is deasserted, whichever occurs ?rst. the link uses rxactive to time high-speed packets and ensure that bus turnaround times are met. for more information on the usb packet timing, see section 10.6.1 . table 22. encoded usb event signals value rxactive rxerror hostdisconnect 00 0 0 0 01 1 0 0 11 1 1 0 10 x x 1
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 36 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.3.4.2 rxerror when the isp1705 has detected an error while receiving a usb packet, it deasserts nxt and sends an rxcmd with the rxerror ?eld set to logic 1. the received packet is no longer valid and must be dropped by the link. 10.3.4.3 hostdisconnect hostdisconnect is encoded into the rxevent ?eld of the rxcmd. hostdisconnect is valid only when the isp1705 is con?gured as a host (both dp_pulldown and dm_pulldown are set to logic 1), and indicates to the host controller when a peripheral is connected (0b) or disconnected (1b). the host controller must enable hostdisconnect by setting the host_discon_r and host_discon_f bits in the usb_intr_en_r and usb_intr_en_f registers, respectively. changes in hostdisconnect will cause the phy to send an rxcmd to the link with the updated value. 10.4 register read and write operations figure 14 shows register read and write sequences. the isp1705 supports immediate addressing and extended addressing register operations. extended register addressing is optional for links. note that register operations will be aborted if the isp1705 asserts dir during the operation. when a register operation is aborted, the link must retry until successful. for more information on register operations, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 10.5 usb reset and high-speed detection handshake (chirp) figure 15 shows the sequence of events for usb reset and high-speed detection handshake (chirp). the sequence is shown for hosts and peripherals. figure 15 does not show all rxcmd updates, and timing is not to scale. the sequence is as follows: ad indicates the address byte, and d indicates the data byte. fig 14. example of register write, register read, extended register write and extended register read clock dir data[7:0] nxt 004aaa710 d txcmd (extw) ad d immediate register write txcmd (regw) txcmd (regr) d ad txcmd (extw) d stp extended register write immediate register read extended register read
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 37 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 1. usb reset: the host detects a peripheral attachment as low-speed if dm is high and as full-speed if dp is high. if a host detects a low-speed peripheral, it does not follow the remainder of this protocol. if a host detects a full-speed peripheral, it resets the peripheral by writing to the func_ctrl register (see section 11.5 ) and setting xcvrselect[1:0] = 00b (high speed) and termselect = 0b that drives se0 on the bus (dp and dm connected to ground through 45 w ). the host also sets opmode[1:0] = 10b for correct chirp transmit and receive. the start of se0 is labeled t0. remark: to receive chirp signaling, the host must also consider the high-speed differential receiver output. the host controller must interpret linestate as shown in t ab le 19 . 2. high-speed detection handshake (chirp) a. peripheral chirp: after detecting se0 for no less than 2.5 m s, if the peripheral is capable of high speed, it sets xcvrselect[1:0] to 00b (high speed) and opmode[1:0] to 10b (chirp). the peripheral immediately follows this with a txcmd (nopid), transmitting a chirp k for no less than 1 ms and ending no more than 7 ms after reset time t0. if the peripheral is in low-power mode, it must wake up its clock within 5.6 ms, leaving 200 m s for the link to start transmitting the chirp k, and 1.2 ms for the chirp k to complete (worst case with 10 % slow clock). b. host chirp: if the host does not detect the peripheral chirp, it must continue asserting se0 until the end of reset. if the host detects the peripheral chirp k for no less than 2.5 m s, then no more than 100 m s after the bus leaves the chirp k state, the host sends a txcmd (nopid) with an alternating sequence of chirp ks and js. each chirp k or chirp j must last no less than 40 m s and no longer than 60 m s. c. high speed idle: the peripheral must detect a minimum of chirp k-j-k-j-k-j. each chirp k and chirp j must be detected for at least 2.5 m s. the peripheral sets termselect = 0b and opmode[1:0] = 00b after seeing the minimum chirp sequence. the peripheral is now in high-speed mode and sees !squelch (01b on linestate). when the peripheral sees squelch (10b on linestate), it knows that the host has completed chirp and waits for hi-speed usb traf?c to begin. after transmitting the chirp sequence, the host changes opmode[1:0] to 00b and begins sending usb packets. for more information, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 .
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 38 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver timing is not to scale. fig 15. usb reset and high-speed detection handshake (chirp) sequence 001aai188 k data [7:0] k j txcmd nopid j ... txcmd (regw) txcmd (regw) se0 k dir 00 stp nxt xcvr select term select 01 (fs) 00 (hs) op mode 00 (normal) 01 (chirp) 00 (normal) line state j (01b) se0 (00b) peripheral chirp k (10b) squelch (00b) host chirp k (10b) or chirp j (01b) squelch (00b) ulpi host k data [7:0] k txcmd nopid k ... se0 txcmd (regw) 00 k j k j k j txcmd (regw) 00 dir stp nxt xcvr select 01 (fs) 00 (hs) term select op mode 00 (normal) 10 (chirp) 00 (normal) line state j (01b) se0 (00b) peripheral chirp k (10b) !squelch (01b) host chirp k or j (10b or 01b) squelch (00b) squelch (00b) dp dm ulpi peripheral usb signals usb reset high-speed detection handshake (chirp) peripheral chirp host chirp hs idle t0 rxcmds
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 39 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.6 usb packet transmit and receive an example of a packet transmit and receive is shown in figure 16 . for details on usb packets, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . 10.6.1 usb packet timing 10.6.1.1 isp1705 pipeline delays the isp1705 delays (in clock cycles) are shown in t ab le 23 . for detailed description, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.2.6.2 . 10.6.1.2 allowed link decision time the amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back packets is given in t ab le 24 . link designs must follow the values given in t ab le 24 for correct usb system operation. examples of high-speed packet sequences and timing are shown in figure 17 and figure 18 . for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.2.6.3 . fig 16. example of using the isp1705 to transmit and receive usb data clock txcmd data data [ 7:0 ] turnaround rxcmd data turnaround dir stp nxt 004aab046 link sends txcmd isp1705 accepts txcmd link sends the next data; isp1705 accepts link signals end of data ulpi bus is idle isp1705 asserts dir, causing turnaround cycle isp1705 sends rxcmd (nxt low) isp1705 sends usb data (nxt high) isp1705 deasserts dir, causing turnaround cycle table 23. phy pipeline delays parameter name high-speed phy delay full-speed phy delay low-speed phy delay rxcmd delay (j and k) 4 4 4 rxcmd delay (se0) 4 4 to 6 16 to 18 tx start delay 1 to 2 6 to 10 74 to 75 tx end delay (packets) 3 to 4 not applicable not applicable tx end delay (sof) 6 to 9 not applicable not applicable rx start delay 5 to 6 not applicable not applicable rx end delay 5 to 6 17 to 18 122 to 123
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 40 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver table 24. link decision times packet sequence high-speed link delay full-speed link delay low-speed link delay de?nition transmit-transmit (host only) 15 to 24 7 to 18 77 to 247 number of clock cycles a host link must wait before driving the txcmd for the second packet. in high speed, the link starts counting from the assertion of stp for the ?rst packet. in full speed, the link starts counting from the rxcmd, indicating linestate has changed from se0 to j for the ?rst packet. the timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. receive-transmit (host or peripheral) 1 to 14 7 to 18 77 to 247 number of clock cycles the link must wait before driving the txcmd for the transmit packet. in high speed, the link starts counting from the end of the receive packet; deassertion of dir or an rxcmd indicating rxactive is low. in full speed or low speed, the link starts counting from the rxcmd, indicating linestate has changed from se0 to j for the receive packet. the timing given ensures inter-packet delays of 2 bit times to 6.5 bit times. receive-receive (peripheral only) 1 1 1 minimum number of clock cycles between consecutive receive packets. the link must be capable of receiving both packets. transmit-receive (host or peripheral) 92 80 718 host or peripheral transmits a packet and will time-out after this number of clock cycles if a response is not received. any subsequent transmission can occur after this time. fig 17. high-speed transmit-to-transmit packet timing 004aaa712 dp or dm data eop idle sync clock d n - 1 d n data [7:0] d0 txcmd d1 dir stp nxt tx end delay (two to five clocks) link decision time (15 to 24 clocks) tx start delay (one to two clocks) usb interpacket delay (88 to 192 high-speed bit times)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 41 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.7 preamble preamble packets are headers to low-speed packets that must travel over a full-speed bus, between a host and a hub. to enter preamble mode, the link sets xcvrselect[1:0] = 11b in the func_ctrl register (see section 11.5 ). when in preamble mode, the isp1705 operates just as in full-speed mode, and sends all data with the full-speed rise time and fall time. whenever the link transmits a usb packet in preamble mode, the isp1705 will automatically send a preamble header at full-speed bit rate before sending the link packet at low-speed bit rate. the isp1705 will ensure a minimum gap of four full-speed bit times between the last bit of the full-speed pre pid and the ?rst bit of the low-speed packet sync. the isp1705 will drive a j for at least one full-speed bit time after sending the pre pid, after which the pull-up resistor can hold the j state on the bus. an example transmit packet is shown in figure 19 . in preamble mode, the isp1705 can also receive low-speed packets from the full-speed bus. fig 18. high-speed receive-to-transmit packet timing 004aaa713 dp or dm data eop idle sync clock d n - 4 d n - 3 data [7:0] d0 txcmd d1 dir stp nxt rx end delay (three to eight clocks) link decision time (1 to 14 clocks) tx start delay (one to two clocks) usb interpacket delay (8 to 192 high-speed bit times) d n - 2 d n - 1 d n turnaround
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 42 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.8 usb suspend and resume 10.8.1 full-speed or low-speed host-initiated suspend and resume figure 20 illustrates how a host or a hub places a full-speed or low-speed peripheral into suspend and sometime later initiates resume signaling to wake-up the downstream peripheral. note that figure 20 timing is not to scale, and does not show all rxcmd linestate updates. the sequence of events for a host and a peripheral, both with isp1705, is as follows: 1. idle: initially, the host and the peripheral are idle. the host has its 15 k w pull-down resistors enabled (dp_pulldown and dm_pulldown are set to 1b) and 45 w terminations are disabled (termselect is set to 1b). the peripheral has the 1.5 k w pull-up resistor connected to dp for full speed or dm for low speed (termselect is set to 1b). 2. suspend: when the peripheral sees no bus activity for 3 ms, it enters the suspend state. the peripheral link places the phy into low-power mode by clearing the suspendm bit in the func_ctrl register (see section 11.5 ), causing the phy to draw only suspend current. the host may or may not be powered down. 3. resume k: when the host wants to wake up the peripheral, it sets opmode[1:0] to 10b and transmits a k for at least 20 ms. the peripheral link sees the resume k on linestate, and asserts stp to wake up the phy. 4. eop: when stp is asserted, the isp1705 on the host side automatically appends an eop of two bits of se0 at low-speed bit rate, followed by one bit of j. the isp1705 on the host side knows to add the eop because dp_pulldown and dm_pulldown are set to 1b for a host. after the eop is completed, the host link sets opmode[1:0] to 00b for normal operation. the peripheral link sees the eop and also resumes normal operation. dp and dm timing is not to scale. fig 19. preamble sequence clock d0 txcmd (low-speed packet id) d1 data[7:0] dir stp nxt 004aaa714 dp or dm fs sync fs pre id idle (min 4 fs bits) ls sync ls pid ls d0 ls d1
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 43 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.8.2 high speed suspend and resume figure 21 illustrates how a host or a hub places a high-speed enabled peripheral into suspend and then initiates resume signaling. the high-speed peripheral will wake up and return to high-speed operations. note that figure 21 timing is not to scale, and does not show all rxcmd linestate updates. timing is not to scale. fig 20. full speed suspend and resume data [ 7:0 ] k txcmd nopid k ... txcmd (regw) dir stp nxt opmode 00b 10b 00b k txcmd line state j k se0 j clock data [ 7:0 ] txcmd (regw) linestate j linestate k se0 j dir stp nxt opmode 00b 10b 00b suspendm line state j k se0 j dp dm 004aab123 fs or ls host (xcvrselect = 01b (fs) or 10b (ls), dp_pulldown = 1b, dm_pulldown = 1b, termselect = 1b) fs or ls peripheral (xcvrselect = 01b (fs) or 10b (ls), dp_pulldown = 0b, termselect = 1b) usb signals (only fs is shown) idle suspend resume k eop idle
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 44 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver the sequence of events related to a host and a peripheral, both with isp1705, is as follows: 1. high speed idle: initially, the host and the peripheral are idle. the host has its 15 k w pull-down resistors enabled (dp_pulldown and dm_pulldown are set to 1b) and 45 w terminations enabled (termselect is set to 0b). the peripheral has its 45 w terminations enabled (termselect is set to 0b). 2. full speed suspend: when the peripheral sees no bus activity for 3 ms, it enters the suspend state. the peripheral link places the isp1705 into full-speed mode (xcvrselect is set to 01b), removes 45 w terminations, and enables the 1.5 k w pull-up resistor on dp (termselect is set to 1b). the peripheral link then places the isp1705 into low-power mode by clearing suspendm, causing the isp1705 to draw only suspend current. the host also changes the isp1705 to full speed, (xcvrselect is set to 01b), removes 45 w terminations (termselect is set to 1b), and then may or may not be powered down. 3. resume k: when the host wants to wake up the peripheral, it sets opmode to 10b and transmits a full-speed k for at least 20 ms. the peripheral link sees the resume k (10b) on linestate, and asserts stp to wake up the isp1705. 4. high-speed traf?c: the host link sets high speed (xcvrselect is set to 00b), and enables its 45 w terminations (termselect is set to 0b). the peripheral link sees se0 on linestate and also sets high speed (xcvrselect is set to 00b), and enables its 45 w terminations (termselect is set to 0b). the host link sets opmode to 00b for normal high-speed operation.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 45 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver timing is not to scale. fig 21. high speed suspend and resume data [ 7:0 ] k txcmd nopid k ... txcmd (regw) dir stp nxt op mode 00b 10b 00b k txcmd (regw) clock data [ 7:0 ] txcmd (regw) linestate j linestate k se0 txcmd (regw) dir stp nxt op mode 00b 10b 00b suspendm line state dp dm 004aab124 ulpi hs host (dp_pulldown = 1b, dm_pulldown = 1b) ulpi hs peripheral (dp_pulldown = 0b) usb signals hs idle fs suspend resume k txcmd (regw) hs idle xcvr select 00b 01b 00b term select line state !squelch (01b) fs j (01b) !squelch (01b) squelch (00b) fs k (10b) xcvr select 00b 01b 00b term select !squelch (01b) squelch (00b) fs j (01b) !squelch (01b) squelch (00b) fs k (10b) squelch (00b)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 46 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.8.3 remote wake-up the isp1705 supports peripherals that initiate remote wake-up resume. when placed into usb suspend, the peripheral link remembers at what speed it was originally operating. depending on the original speed, the link follows one of the protocols detailed here. in figure 22 , timing is not to scale, and not all rxcmd linestate updates are shown. the sequence of events related to a host and a peripheral, both with isp1705, is as follows: 1. both the host and the peripheral are assumed to be in low-power mode. 2. the peripheral begins remote wake-up by re-enabling its clock and setting its suspendm bit to 1b. 3. the peripheral begins driving k on the bus to signal resume. note that the peripheral link must assume that linestate is k (01b) while transmitting because it will not receive any rxcmds. 4. the host recognizes the resume, re-enables its clock and sets its suspendm bit. 5. the host takes over resume driving within 1 ms of detecting the remote wake-up. 6. the peripheral stops driving resume. 7. the peripheral sees the host continuing to drive the resume. 8. the host stops driving resume and the isp1705 automatically adds the eop to the end of the resume. the peripheral recognizes the eop as the end of resume. 9. both the host and the peripheral revert to normal operation by writing 00b to opmode. if the host or the peripheral was previously in high-speed mode, it must revert to high speed before the se0 of the eop is completed. this can be achieved by writing xcvrselect[1:0] = 00b and termselect = 0b after linestate indicates se0.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 47 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.9 no automatic sync and eop generation (optional) this setting allows the link to turn off the automatic sync and eop generation, and must be used for high-speed packets only. it is provided for backwards compatibility with legacy controllers that include sync and eop bytes in the data payload when transmitting packets. the isp1705 will not automatically generate sync and eop patterns when opmode[1:0] is set to 11b. the isp1705 will still nrzi encode data and perform bit stuf?ng. an example of a sequence is shown in figure 23 . the link must always send packets using the txcmd (nopid) type. the isp1705 does not provide a mechanism to control bit stuf?ng in individual bytes, but will automatically turn off bit stuf?ng for eop when stp is asserted with data set to feh. if data is set to 00h when stp is asserted, the timing is not to scale. fig 22. remote wake-up from low-power mode data [ 7:0 ] linestate txcmd regw txcmd regw 00h txcmd nopid dir stp nxt xcvr select 01b (fs), 10b (ls) 00b (hs only) term select op mode 10b 00b data [ 7:0 ] linestate txcmd regw rxcmd 00h txcmd nopid rxcmd rxcmd txcmd regw dir stp nxt xcvr select 00b (hs), 01b (fs), 10b (ls) 00b (hs only) term select op mode 10b 00b ulpi host ulpi peripheral 004aaa718 0b (hs only) 0b (hs only)
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 48 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver phy will not transmit any eop. the isp1705 will also detect if the pid byte is a5h, indicating an sof packet, and automatically send a long eop when stp is asserted. to transmit chirp and resume signaling, the link must set opmode to 10b. 10.10 on-the-go operations on-the-go (otg) is a supplement to universal serial bus speci?cation rev. 2.0 that allows a portable usb device to assume the role of a limited usb host by de?ning improvements, such as a small connector and low power. non-portable devices, such as standard hosts and embedded hosts, can also bene?t from otg features. the isp1705 otg phy is designed to support all the tasks speci?ed in the otg supplement. the isp1705 provides the front end analog support for host negotiation protocol (hnp) and session request protocol (srp) for dual-role devices. the supporting components include: ? voltage comparators C a_vbus_vld C sess_vld (session valid, can be used for both a-session and b-session valid) C sess_end (session end) ? pull-up and pull-down resistors on dp and dm ? id detector indicates if micro-a or micro-b plug is inserted ? charge and discharge resistors on v bus the following subsections describe how to use the isp1705 otg components. fig 23. transmitting usb packets without automatic sync and eop generation clock data [7:0] txcmd 00h 00h 00h 80h pid d1 d2 d3 ... ... d n - 1 feh d n dir stp nxt ulpi signals txvalid txready txbit stuff enable dp, dm idle sync pid idle eop data payload 004aab125 utmi+ equivalent signals usb bus
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 49 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.10.1 otg comparators the isp1705 provides comparators that conform to on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 requirements of v a_vbus_vld , v a_sess_vld , v b_sess_vld and v b_sess_end . in this data sheet, v a_sess_vld and v b_sess_vld are combined into v a_sess_vld . comparators are described in section 8.7.2 . changes in comparator values are communicated to the link by rxcmds as described in section 10.3.2 . control over comparators is described in section 11.8 to section 11.11 . 10.10.2 pull-up and pull-down resistors the usb resistors on dp and dm can be used to initiate data-line pulsing srp. the link must set the required bus state using the mode settings in t ab le 15 . 10.10.3 id detection the isp1705 provides an internal pull-up resistor to sense the state of the id pin. the pull-up resistor must ?rst be enabled by setting the id_pullup register bit to logic 1. if the state of pin id has changed, the isp1705 will send an rxcmd or interrupt to the link by time t id . if the link does not receive any rxcmd or interrupt by t id , then the id state has not changed. 10.10.4 v bus charge and discharge resistors a pull-up resistor, r up(vbus) , is provided to perform v bus pulsing srp. a b-device is allowed to charge v bus above the session valid threshold to request the host to turn on the v bus voltage. a pull-down resistor, r dn(vbus) , is provided for a b-device to discharge v bus . this is done whenever the a-device turns off the v bus voltage; the b-device can use the pull-down resistor to ensure v bus is below v b_sess_end before starting a session. for details, refer to on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 . 10.11 serial modes the isp1705 supports both 6-pin serial mode and 3-pin serial mode, controlled by bits 6pin_fsls_serial and 3pin_fsls_serial of the intf_ctrl register (see section 11.6 ). for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.10 . figure 24 and figure 25 provide examples of 6-pin serial mode and 3-pin serial mode, respectively.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 50 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver fig 24. example of transmit followed by receive in 6-pin serial mode data0 (tx_enable) data1 (tx_dat) data2 (tx_se0) data4 (rx_dp) data5 (rx_dm) data6 (rx_rcv) dp dm sync data eop transmit receive sync data eop 004aaa692 fig 25. example of transmit followed by receive in 3-pin serial mode data0 (tx_enable) data1 (tx_dat/ rx_rcv) dp data2 (tx_se0/ rx_se0) dm 004aaa693 sync data eop transmit receive sync data eop
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 51 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 10.12 aborting transfers the isp1705 supports aborting transfers on the ulpi bus. for details, refer to utmi+ low pin interface (ulpi) speci?cation rev. 1.1, section 3.8.4 . 10.13 avoiding contention on the ulpi data bus because the ulpi data bus is bidirectional, avoid situations in which both the link and the phy simultaneously drive the data bus. the following points must be considered while implementing the data bus drive control on the link. after power-up and clock stabilization, default states are as follows: ? the isp1705 drives dir to low. ? the data bus is input to the isp1705. ? the ulpi link data bus is output, with all data bus lines driven to low. when the isp1705 wants to take control of the data bus to initiate a data transfer, it changes the dir state from low to high. at this point, the link must disable its output buffers. this must be as fast as possible so the link must use a combinational path from dir. the isp1705 will not immediately enable its output buffers, but will delay the enabling of its buffers until the next clock edge, avoiding bus contention. when the data transfer is no longer required by the isp1705, it changes dir from high to low and starts to immediately turn off its output drivers. the link senses the change of dir from high to low, but delays enabling its output buffers for one clock cycle, avoiding data bus contention.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 52 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11. register map [1] read (r): a register can be read. read-only if this is the only mode given. [2] write (w): the pattern on the data bus will be written over all bits of a register. [3] set (s): the pattern on the data bus is or-ed with and written to a register. [4] clear (c): the pattern on the data bus is a mask. if a bit in the mask is set, then the corresponding register bit will be s et to zero (cleared). 11.1 vendor_id_low register t ab le 26 shows the bit description of the register. 11.2 vendor_id_high register t ab le 27 shows the bit description of the register. table 25. register map field name size (bit) address (6 bit) references r [1] w [2] s [3] c [4] vendor_id_low 8 00h - - - section 11.1 on page 52 vendor_id_high 8 01h - - - section 11.2 on page 52 product_id_low 8 02h - - - section 11.3 on page 53 product_id_high 8 03h - - - section 11.4 on page 53 func_ctrl 8 04h to 06h 04h 05h 06h section 11.5 on page 53 intf_ctrl 8 07h to 09h 07h 08h 09h section 11.6 on page 55 otg_ctrl 8 0ah to 0ch 0ah 0bh 0ch section 11.7 on page 56 usb_intr_en_r 8 0dh to 0fh 0dh 0eh 0fh section 11.8 on page 58 usb_intr_en_f 8 10h to 12h 10h 11h 12h section 11.9 on page 58 usb_intr_stat 8 13h - - - section 11.10 on page 59 usb_intr_l 8 14h - - - section 11.11 on page 59 debug 8 15h - - - section 11.12 on page 60 scratch 8 16h to 18h 16h 17h 18h section 11.13 on page 61 carkit_ctrl 8 19h to 1bh 19h 1ah 1bh section 11.14 on page 61 reserved 8 1ch to 3ch - - - - pwr_ctrl 8 3dh to 3fh 3dh 3eh 3fh section 11.15 on page 62 table 26. vendor_id_low - vendor id low register (address r = 00h) bit description legend: * reset value bit symbol access value description 7 to 0 vendor_ id_low[7:0] r cch* vendor id low : lower byte of the nxp vendor id supplied by usb-if; ?xed value of cch table 27. vendor_id_high - vendor id high register (address r = 01h) bit description legend: * reset value bit symbol access value description 7 to 0 vendor_ id_high[7:0] r 04h* vendor id high : upper byte of the nxp vendor id supplied by usb-if; ?xed value of 04h
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 53 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.3 product_id_low register the bit description of the register is given in t ab le 28 . 11.4 product_id_high register the bit description of the register is given in t ab le 29 . 11.5 func_ctrl register this register controls utmi function settings of the phy. the bit allocation of the register is given in t ab le 30 . table 28. product_id_low - product id low register (address r = 02h) bit description legend: * reset value bit symbol access value description 7 to 0 product_id_ low[7:0] r 05h* product id low : lower byte of the nxp product id number; ?xed value of 05h table 29. product_id_high - product id high register (address r = 03h) bit description legend: * reset value bit symbol access value description 7 to 0 product_id_ high[7:0] r 17h* product id high : upper byte of the nxp product id number; ?xed value of 17h table 30. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved suspendm reset opmode[1:0] term select xcvrselect[1:0] reset 01 000001 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 31. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit description bit symbol description 7 - reserved 6 suspendm suspend : active-low phy suspend. places the phy into low-power mode. the phy will power down all blocks, except the full-speed receiver, otg comparators and ulpi interface pins. to come out of low-power mode, the link must assert stp. the phy will automatically clear this bit when it exits low-power mode. 0b low-power mode 1b powered 5 reset reset : active-high transceiver reset. after the link sets this bit, the phy will assert dir and reset the digital core. this does not reset the ulpi interface or the ulpi register set. when the reset is completed, the phy will deassert dir and automatically clear this bit, followed by an rxcmd update to the link. the link must wait for dir to be deasserted before using the ulpi bus. 0b do not reset 1b reset
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 54 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 4 to 3 opmode[1:0] operation mode : selects the required bit-encoding style during transmit. 00b normal operation 01b non-driving 10b disable bit-stuf?ng and nrzi encoding 11b do not automatically add sync and eop when transmitting; must be used only for high-speed packets 2 termselect termination select : controls the internal 1.5 k w full-speed pull-up resistor and 45 w high-speed terminations. control over bus resistors changes, depending on xcvrselect[1:0], opmode[1:0], dp_pulldown and dm_pulldown, as shown in t ab le 15 . 1 to 0 xcvrselect[1:0] transceiver select : selects the required transceiver speed. 00b enable the high-speed transceiver 01b enable the full-speed transceiver 10b enable the low-speed transceiver 11b enable the full-speed transceiver for low-speed packets (full-speed preamble is automatically pre?xed) table 31. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit description continued bit symbol description
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 55 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.6 intf_ctrl register the intf_ctrl register enables alternative interfaces. all of these modes are optional features provided for legacy link cores. setting more than one of these ?elds results in unde?ned behavior. t ab le 32 provides the bit allocation of the register. table 32. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit allocation bit 7 6 5 4 3 2 1 0 symbol intf_ prot_dis ind_pass thru ind_ compl reserved clock_ suspendm carkit_ mode 3pin_ fsls_ serial 6pin_ fsls_ serial reset 0 0000 000 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 33. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit description bit symbol description 7 intf_prot_dis interface protect disable : controls circuitry built into the isp1705 to protect the ulpi interface when the link 3-states stp and data[7:0]. when this bit is enabled, the isp1705 will automatically detect when the link stops driving stp. 0b enables the interface protect circuit. the isp1705 attaches a weak pull-up resistor on stp. if stp is unexpectedly high, the isp1705 attaches weak pull-down resistors on data[7:0], protecting data inputs 1b disables the interface protect circuit, detaches weak pull-down resistors on data[7:0], and a weak pull-up resistor on stp 6 ind_passthru indicator pass-through : controls whether the complement output is quali?ed with the internal a_vbus_vld comparator before being used in the v bus state in rxcmd. 0b the complement output signal is quali?ed with the internal a_vbus_vld comparator 1b the complement output signal is not quali?ed with the internal a_vbus_vld comparator 5 ind_compl indicator complement : informs the phy to invert the fault input signal, generating the complement output. 0b the isp1705 will not invert the fault signal 1b the isp1705 will invert the fault signal 4 - reserved 3 clock_suspendm clock suspend : active-low clock suspend. powers down the internal clock circuitry only. by default, the clock will not be powered in 6-pin serial mode or 3-pin serial mode. valid only in 6-pin serial mode and 3-pin serial mode. valid only when suspendm is set to logic 1, otherwise this bit is ignored. 0b clock will not be powered in 3-pin or 6-pin serial mode or uart mode 1b clock will be powered in 3-pin and 6-pin serial mode or uart mode
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 56 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.7 otg_ctrl register this register controls various otg functions of the isp1705. the bit allocation of the otg_ctrl register is given in t ab le 34 . [1] a weak pull-up, which can detect id correctly, is present when the id_pullup bit is disabled. it is, however, mandatory that the link enables id_pullup. 2 carkit_mode carkit mode : changes the ulpi interface to the carkit interface (uart mode). bits txd_en and rxd_en in the carkit_ctrl register (see section 11.14 ) must change as well. the phy must automatically clear this bit when carkit mode is exited. 0b disable carkit mode 1b enable carkit mode 1 3pin_fsls_serial 3-pin full-speed low-speed serial mode : changes the ulpi interface to a 3-bit serial interface. the isp1705 will automatically clear this bit when 3-pin serial mode is exited. 0b full-speed or low-speed packets are sent using the parallel interface 1b full-speed or low-speed packets are sent using the 3-pin serial interface 0 6pin_fsls_serial 6-pin full-speed low-speed serial mode : changes the ulpi interface to a 6-bit serial interface. the isp1705 will automatically clear this bit when 6-pin serial mode is exited. 0b full-speed or low-speed packets are sent using the parallel interface 1b full-speed or low-speed packets are sent using the 6-pin serial interface table 33. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit description continued bit symbol description table 34. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit allocation bit 7 6 5 4 3 2 1 0 symbol use_ext_ vbus_ind drv_ vbus_ext reserved chrg_ vbus dischrg_ vbus dm_pull down dp_pull down id_pull up [1] reset 00000110 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 57 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver table 35. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit description bit symbol description 7 use_ext_ vbus_ind use external v bus indicator : informs the phy to use an external v bus overcurrent indicator. 0b use the internal otg comparator 1b use the external v bus valid indicator signal input from the fault pin 6 drv_vbus_ext drive v bus external : controls the external charge pump or 5 v supply by the psw_n pin. 0b psw_n is high 1b psw_n to low 5 reserved - 4 chrg_vbus charge v bus : charges v bus through a resistor. used for the v bus pulsing of srp. the link must ?rst check that v bus is discharged (see bit dischrg_vbus), and that both the dp and dm data lines have been low (se0) for 2 ms. 0b do not charge v bus 1b charge v bus 3 dischrg_vbus discharge v bus : discharges v bus through a resistor. if the link sets this bit to logic 1, it waits for an rxcmd indicating that sess_end has changed from logic 0 to logic 1, and then resets this bit to logic 0 to stop the discharge. 0b do not discharge v bus 1b discharge v bus 2 dm_pulldown dm pull down : enables the 15 k w pull-down resistor on dm. 0b pull-down resistor is not connected to dm 1b pull-down resistor is connected to dm 1 dp_pulldown dp pull down : enables the 15 k w pull-down resistor on dp. 0b pull-down resistor is not connected to dp 1b pull-down resistor is connected to dp 0 id_pullup id pull up : connects a pull-up to the id line and enables sampling of the id level. disabling the id line sampler will reduce the phy power consumption. 0b disable sampling of the id line 1b enable sampling of the id line
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 58 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.8 usb_intr_en_r register the bits in this register enable interrupts and rxcmds to be sent when the corresponding bits in the usb_intr_stat register change from logic 0 to logic 1. by default, all transitions are enabled. t ab le 36 shows the bit allocation of the register. 11.9 usb_intr_en_f register the bits in this register enable interrupts and rxcmds to be sent when the corresponding bits in the usb_intr_stat register change from logic 1 to logic 0. by default, all transitions are enabled. see t ab le 38 . table 36. usb_intr_en_r - usb interrupt enable rising register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_r sess_ end_r sess_ valid_r vbus_ valid_r host_ discon_r reset 00011111 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 37. usb_intr_en_r - usb interrupt enable rising register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit description bit symbol description 7 to 5 - reserved 4 id_gnd_r id ground rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on id_gnd 3 sess_end_r session end rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on sess_end 2 sess_valid_r session valid rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on sess_vld 1 vbus_valid_r v bus valid rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on a_vbus_vld 0 host_discon_r host disconnect rise : enables interrupts and rxcmds for logic 0 to logic 1 transitions on host_discon table 38. usb_intr_en_f - usb interrupt enable falling register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_f sess_ end_f sess_ valid_f vbus_ valid_f host_ discon_f reset 00011111 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 59 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.10 usb_intr_stat register this register (see t ab le 40 ) indicates the current value of the interrupt source signal. 11.11 usb_intr_l register the bits of the usb_intr_l register are automatically set by the isp1705 when an unmasked change occurs on the corresponding interrupt source signal. the isp1705 will automatically clear all bits when the link reads this register, or when the phy enters low-power mode. remark: it is optional for the link to read this register when the clock is running because all signal information will automatically be sent to the link through the rxcmd byte. the bit allocation of this register is given in t ab le 42 . table 39. usb_intr_en_f - usb interrupt enable falling register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit description bit symbol description 7 to 5 - reserved 4 id_gnd_f id ground fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on id_gnd. 3 sess_end_f session end fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on sess_end. 2 sess_valid_f session valid fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on sess_vld. 1 vbus_valid_f v bus valid fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on a_vbus_vld. 0 host_discon_f host disconnect fall : enables interrupts and rxcmds for logic 1 to logic 0 transitions on host_discon. table 40. usb_intr_stat - usb interrupt status register (address r = 13h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd sess_ end sess_ valid vbus_ valid host_ discon reset xxx00000 access rrrrrrrr table 41. usb_intr_stat - usb interrupt status register (address r = 13h) bit description bit symbol description 7 to 5 - reserved 4 id_gnd id ground : re?ects the current state of the id detector circuit. 3 sess_end session end : re?ects the current value of the session end voltage comparator. 2 sess_valid session valid : re?ects the current value of the session valid voltage comparator. 1 vbus_valid v bus valid : re?ects the current value of the v bus valid voltage comparator. 0 host_discon host disconnect : re?ects the current value of the host disconnect detector.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 60 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.12 debug register the bit allocation of the debug register is given in t ab le 44 . this register indicates the current value of signals useful for debugging. table 42. usb_intr_l - usb interrupt latch register (address r = 14h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved id_gnd_l sess_ end_l sess_ valid_l vbus_ valid_l host_ discon_l reset 00000000 access rrrrrrrr table 43. usb_intr_l - usb interrupt latch register (address r = 14h) bit description bit symbol description 7 to 5 reserved - 4 id_gnd_l id ground latch : automatically set when an unmasked event occurs on id_gnd. cleared when this register is read. 3 sess_end_l session end latch : automatically set when an unmasked event occurs on sess_end. cleared when this register is read. 2 sess_valid_l session valid latch : automatically set when an unmasked event occurs on sess_vld. cleared when this register is read. 1 vbus_valid_l v bus valid latch : automatically set when an unmasked event occurs on a_vbus_vld. cleared when this register is read. 0 host_discon_l host disconnect latch : automatically set when an unmasked event occurs on host_discon. cleared when this register is read. table 44. debug - debug register (address r = 15h) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved line state1 line state0 reset 00000000 access rrrrrrrr table 45. debug - debug register (address r = 15h) bit description bit symbol description 7 to 2 - reserved 1 linestate1 line state 1 : contains the current value of linestate 1 0 linestate0 line state 0 : contains the current value of linestate 0
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 61 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.13 scratch register this is a 1-byte empty register for testing purposes, see t ab le 46 . 11.14 carkit_ctrl register this register controls transparent uart mode. this register is only valid when the carkit_mode bit in the intf_ctrl register (see section 11.6 ) is set. when entering uart mode, set the carkit_mode bit, and then set the txd_en and rxd_en bits. after entering uart mode, the ulpi interface is not available. when exiting uart mode, assert the stp pin or perform a hardware reset using chip select. for bit allocation, see t ab le 47 . table 46. scratch - scratch register (address r = 16h to 18h, w = 16h, s = 17h, c = 18h) bit description bit symbol access value description 7 to 0 scratch[7:0] r/w/s/c 00h scratch : this is an empty register byte for testing purposes. software can read, write, set and clear this register. the functionality of the phy will not be affected. table 47. carkit_ctrl - carkit control register (address r = 19h to 1bh, w = 19h, s = 1ah, c = 1bh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved rxd_en txd_en reserved reset 00000000 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 48. carkit_ctrl - carkit control register (address r = 19h to 1bh, w = 19h, s = 1ah, c = 1bh) bit description bit symbol description 7 to 4 - reserved; the link must never write logic 1 to these bits 3 rxd_en rxd enable : routes the uart rxd signal from the dp pin to the data1 pin. this bit will automatically be cleared when uart mode is exited. 2 txd_en txd enable : routes the uart txd signal from the data0 pin to the dm pin. this bit will automatically be cleared when uart mode is exited. 1 to 0 - reserved; the link must never write logic 1 to these bits
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 62 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 11.15 pwr_ctrl register this vendor-speci?c register controls the power feature of the isp1705. the bit allocation of the register is given in t ab le 49 . table 49. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit allocation bit 7 6 5 4 3 2 1 0 symbol reserved dp_wkpu_ en bvalid_ fall bvalid_ rise reserved reset 0000 0000 access r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c r/w/s/c table 50. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit description bit symbol description 7 to 5 - reserved; the link must never write logic 1 to these bits 4 dp_wkpu_en dp weak pull-up enable : enable the weak pull-up resistor on the dp pin (r weakup(dp) ) in synchronous mode when v bus is above the v a_sess_vld threshold. note that when the isp1705 is in uart mode, the dp weak pull-up will be enabled, regardless of the value of this register bit. 0 dp weak pull-up is disabled. 1 dp weak pull-up is enabled when v bus > v a_sess_vld . 3 bvalid_fall bvalid fall : enables rxcmds for high-to-low transitions on bvalid. when bvalid changes from high to low, the isp1705 will send an rxcmd to the link with the alt_int bit set to logic 1. this bit is optional and is not necessary for otg devices. this bit is provided for debugging purposes. disabled by default. 2 bvalid_rise bvalid rise : enables rxcmds for low-to-high transitions on bvalid. when bvalid changes from low to high, the isp1705 will send an rxcmd to the link with the alt_int bit set to logic 1. this bit is optional and is not necessary for otg devices. this bit is provided for debugging purposes. disabled by default. 1 to 0 - reserved; the link must never write logic 1 to these bits
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 63 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 12. limiting values [1] the isp1705 has been tested according to the additional requirements listed in universal serial bus speci?cation rev. 2.0, section 7.1.1 . the short circuit withstand test and the ac stress test were performed for 24 hours, and the isp1705 was found to be fully operational after the test completed. [2] when an external series resistor is added to the v bus pin, it can withstand higher voltages for longer periods of time because the resistor limits the current ?owing into the v bus pad. for example, with an external 1 k w resistor, v bus can tolerate 10 v for at least 5 seconds. actual performance may vary depending on the resistor used and whether other components are connected to v bus . [3] the isp1705 has been tested in-house according to the iec 61000-4-2 standard on the dp and dm pins. it is recommended that customers perform their own esd tests, depending on application requirements. 13. recommended operating conditions table 51. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cc supply voltage - 0.5 +5.5 v v cc(i/o) input/output supply voltage - 0.5 +4.6 v v i input voltage on pins psw_n and fault - 0.5 +5.5 v on pins clock, stp, data[7:0], cfg1, cfg2, reset_n, chip_sel and chip_sel_n - 0.5 v cc(i/o) + 0.5 v on pins id and cfg0 - 0.5 +4.6 v on pin xtal1 - 0.5 +2.5 v on pins dp and dm [1] - 0.5 +4.6 v on pin v bus [2] - 0.5 +5.5 v v esd electrostatic discharge voltage human body model (jesd22-a114d) - 2+2 kv machine model (jesd22-a115-a) - 200 +200 v charged device model (jesd22-c101-c) - 500 +500 v iec 61000-4-2 contact on pins dp and dm [3] - 8+8 kv i lu latch-up current - 100 ma t stg storage temperature - 60 +125 c table 52. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 3.0 3.6 4.5 v v cc(i/o) input/output supply voltage 3.0 3.3 3.6 v v i input voltage on pins psw_n, fault and v bus 0 - 5.25 v on pins clock, stp, data[7:0], cfg1, cfg2, reset_n, chip_sel and chip_sel_n 0- v cc(i/o) v on pins dp, dm, id and cfg0 0 - 3.6 v on pin xtal1 0 - 1.95 v t j junction temperature - 40 - +125 c t amb ambient temperature - 40 +25 +85 c
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 64 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 14. static characteristics [1] the actual value of i cc(i/o) varies depending on the capacitance loading, interface voltage and bus activity. use the value provided here only as a reference. table 53. static characteristics: supply pins v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v por(trip) power-on reset trip voltage on reg1v8 pin 0.95 - 1.5 v i cc supply current power-down mode (v cc(i/o) is lost or chip select is non-active) - 0.5 10 m a full-speed transceiver; bus idle; no usb activity -13-ma full-speed transceiver; 100 % transmission; no inter-packet delay - 25.65 - ma high-speed transceiver; 100 % transmission; no inter-packet delay - 55.30 - ma low-power mode (bit suspendm is logic 0); v bus valid detector disabled (bits vbus_valid_r and vbus_valid_f are cleared) for host - 70 100 m a for peripheral - 240 330 m a uart mode; low-speed transceiver; idle - 750 - m a uart mode; full-speed transceiver; idle - 600 - m a i cc(i/o)(stat) static supply current on pin v cc(i/o) power-down mode (chip select is non-active) --10 m a i cc(i/o) supply current on pin v cc(i/o) ulpi bus idle; 15 pf load on pin clock [1] -2-ma table 54. static characteristics: digital pins digital pins: clock, dir, stp, nxt, data[7:0], chip_sel_n, chip_sel, cfg1, cfg2 and reset_n; unless otherwise speci?ed. v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v ih high-level input voltage 0.7v cc(i/o) -- v v il low-level input voltage - - 0.3v cc(i/o) v i li input leakage current - 1-+1 m a output levels v oh high-level output voltage i ol = +2 ma v cc(i/o) - 0.4 - - v
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 65 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] when v oh is less than v o(reg3v3) , i cc may increase because of the cross current. v ol low-level output voltage i oh = - 2 ma - - 0.4 v i oh high-level output current v oh = v cc(i/o) - 0.4 v 8 - - ma i ol low-level output current v ol = 0.4 v 8 - - ma impedance z l load impedance 45 - 65 w pull-up and pull-down i pu pull-up current interface protect enabled; stp pin only; v i =0v - 30 - 50 - 80 m a uart mode; data0 pin only - 30 - 50 - 80 m a i pd pull-down current interface protect enabled; data[7:0] pins only; v i =v cc(i/o) 25 50 95 m a capacitance c in input capacitance - - 2.9 pf table 54. static characteristics: digital pins continued digital pins: clock, dir, stp, nxt, data[7:0], chip_sel_n, chip_sel, cfg1, cfg2 and reset_n; unless otherwise speci?ed. v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 55. static characteristics: digital input pin fault v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v i il low-level input current v i = 0 v - 1-- m a i ih high-level input current v i = 5.25 v - - 1 m a table 56. static characteristics: digital output pin psw_n v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v oh high-level output voltage external pull-up resistor connected 3.0 [1] - 5.25 v v ol low-level output voltage i ol = - 4 ma - - 0.4 v i oh high-level output current external pull-up resistor connected - - 1 m a i ol low-level output current v o = 0.4 v 4.0 - - ma table 57. static characteristics: analog pins (dp, dm) v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit original usb transceiver (full speed and low speed) input levels (differential data receiver) v di differential input sensitivity voltage | v dp - v dm | 0.2 - - v
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 66 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver v cm differential common mode voltage range includes v di range 0.8 - 2.5 v input levels (single-ended receivers) v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v output levels v ol low-level output voltage pull-up on dp; r l = 1.5 k w to 3.6 v 0.0 - 0.3 v v oh high-level output voltage pull-down on pins dp and dm; r l =15k w to gnd 2.8 - 3.6 v v crs output signal crossover voltage excluding the ?rst transition from the idle state 1.3 - 2.0 v termination v term termination voltage for upstream facing port pull-up for 1.5 k w pull-up resistor 3.0 - 3.6 v resistance r up(dp) pull-up resistance on pin dp 1425 1500 1575 w r weakup(dp) weak pull-up resistance on pin dp bit dp_wkpu_en = 1 and v bus > v a_sess_vld 100 125 150 k w hi-speed usb transceiver (hs) input levels v hssq high-speed squelch detection threshold voltage (differential signal amplitude) 100 - 150 mv v hsdsc high-speed disconnect detection threshold voltage (differential signal amplitude) 525 - 625 mv v hsdi high-speed differential input sensitivity | v dp - v dm | 300 - - mv v hscm high-speed data signaling common mode voltage range (guideline for receiver) includes v di range - 50 - +500 mv output levels v hsoi high-speed idle level voltage - 10 - +10 mv v hsol high-speed data signaling low-level voltage - 10 - +10 mv v hsoh high-speed data signaling high-level voltage 360 - 440 mv v chirpj chirp j level (differential voltage) 700 - 1100 mv v chirpk chirp k level (differential voltage) - 900 - - 500 mv leakage current i lz off-state leakage current - 1.0 - +1.0 m a capacitance c in input capacitance pin to gnd - - 5 pf table 57. static characteristics: analog pins (dp, dm) continued v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 67 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver resistance r dn(dp) pull-down resistance on pin dp 14.25 15 15.75 k w r dn(dm) pull-down resistance on pin dm 14.25 15 15.75 k w termination z o(drv)(dp) driver output impedance on pin dp steady-state drive 40.5 45 49.5 w z o(drv)(dm) driver output impedance on pin dm steady-state drive 40.5 45 49.5 w z inp input impedance exclusive of pull-up/pull-down (for low-/full-speed) 1--m w uart mode input levels v il low-level input voltage pin dp - - 0.8 v v ih high-level input voltage pin dp 2.35 - - v output levels v ol low-level output voltage pin dm; i ol = - 4 ma - - 0.3 v v oh high-level output voltage pin dm; i oh =+4ma 2.4 - - v table 57. static characteristics: analog pins (dp, dm) continued v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit table 58. static characteristics: analog pin v bus v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit comparators v a_vbus_vld a-device v bus valid voltage 4.4 - 4.75 v v a_sess_vld a-device session valid voltage for a-device and b-device 0.8 1.6 2.0 v v hys(a_sess_vld) a-device session valid hysteresis voltage for a-device and b-device - 100 - mv v b_sess_end b-device session end voltage 0.2 - 0.8 v resistance r up(vbus) pull-up resistance on pin v bus connect to reg3v3 when chrg_vbus = 1 281 680 - w r dn(vbus) pull-down resistance on pin v bus connect to gnd when dischrg_vbus = 1 656 1200 - w r i(idle)(vbus) idle input resistance on pin v bus not in power-down mode 75 90 100 k w chip deasserted (power-down mode) 40 - 100 k w v cc(i/o) lost (power-down mode) 140 - 220 k w
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 68 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver table 59. static characteristics: analog pin cfg0 v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit input levels v il low-level input voltage - - 0.8 v v ih high-level input voltage 2.0 - - v i li input leakage current - 1- +1 m a table 60. static characteristics: id detection circuit v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t id id detection time 50 - - ms v th(id) id detector threshold voltage 1.0 - 2.0 v r up(id) id pull-up resistance bit id_pullup = 1 40 50 60 k w r weakpu(id) weak pull-up resistance on pin id bit id_pullup = 0 320 400 480 k w v pu(id) pull-up voltage on pin id 3.0 3.3 3.6 v table 61. static characteristics: resistor reference v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. suspendm = high. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v o(rref) output voltage on pin rref - 1.22 - v table 62. static characteristics: regulator v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. suspendm = high. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v o(reg1v8) output voltage from internal 1.8 v regulator 1.65 1.8 1.95 v v o(reg3v3) output voltage from internal 3.3 v regulator not in uart mode 3.0 3.3 3.6 v in uart mode 2.5 2.77 2.9 v table 63. static characteristics: pin xtal1 v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit v il low-level input voltage - - 0.37 v v ih high-level input voltage 1.32 - - v
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 69 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 15. dynamic characteristics [1] the internal pll is triggered only on the positive edge from the crystal oscillator. therefore, the duty cycle is not critic al. table 64. dynamic characteristics: reset and power v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t w(por) internal power-on reset pulse width 0.2 - - m s t w(reg1v8_h) reg1v8 high pulse width - - 2 m s t w(reg1v8_l) reg1v8 low pulse width - - 11 m s t w(reset_n) external reset_n pulse width 200 - - ns t startup(pll) pll start-up time measured after t d(det)clk(osc) - - 640 m s t d(det)clk(osc) oscillator clock detector delay measured from regulator start-up time - - 640 m s t pwrup regulator start-up time 4.7 m f 20 % capacitor each on the reg1v8 and reg3v3 pins -- 1 ms t pwrdn regulator power-down time 4.7 m f 20 % capacitor each on the reg1v8 and reg3v3 pins - - 100 ms table 65. dynamic characteristics: clock applied to xtal1 v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit f i(xtal1) input frequency on pin xtal1 see t ab le 6 - 26.000 - mhz see t ab le 6 - 24.000 - mhz see t ab le 6 - 19.300 - mhz see t ab le 6 - 13.000 - mhz t jit(i)(xtal1)rms rms input jitter on pin xtal1 - - 200 ps d f i(xtal1) input frequency tolerance on pin xtal1 - - 200 ppm d i(xtal1) input duty cycle on pin xtal1 for the ?rst transaction [1] -50- % t r(xtal1) rise time on pin xtal1 only for square wave input - - 5 ns t f(xtal1) fall time on pin xtal1 only for square wave input - - 5 ns table 66. dynamic characteristics: clock output v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit f o(av)(clock) average output frequency on pin clock 59.970 60.000 60.030 mhz t jit(o)(clock)rms rms output jitter on pin clock - - 500 ps d o(clock) output clock duty cycle on pin clock 45 50 55 %
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 70 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [1] load capacitance on each ulpi pin. [1] note that the value exceeds that speci?ed in utmi+ low pin interface (ulpi) speci?cation rev. 1.1 . [2] also with respect to the falling edge of pin clock . [3] load capacitance on each ulpi pin. table 67. dynamic characteristics: digital i/o pins (sdr) v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see figure 30 . typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t su(stp) stp set-up time with respect to the rising edge of pin clock input-only pin (stp) 6.0 - - ns t su(data) data set-up time with respect to the rising edge of pin clock bidirectional pins (data[7:0]) as inputs 6.0 - - ns t h(stp) stp hold time with respect to the rising edge of pin clock input-only pin (stp) 0.0 - - ns t h(data) data hold time with respect to the rising edge of pin clock bidirectional pins (data[7:0]) as inputs 0.0 - - ns t d(dir) dir output delay with respect to the rising edge of pin clock output-only pin dir - - 9.0 ns t d(nxt) nxt output delay with respect to the rising edge of pin clock output-only pin nxt - - 9.0 ns t d(data) data output delay with respect to the rising edge of pin clock bidirectional pins as output (data[7:0]) - - 9.0 ns c l load capacitance pins data[7:0], clock, dir, nxt, stp [1] --20pf table 68. dynamic characteristics: digital i/o pins (ddr) v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. see figure 30 . symbol parameter conditions min typ max unit t su(stp) stp set-up time with respect to the rising edge of pin clock input-only pin (stp) 6.0 - - ns t su(data) data set-up time with respect to the rising edge of pin clock bidirectional pins (data[3:0]) as inputs [1] [2] 4.0 - - ns t h(stp) stp hold time with respect to the rising edge of pin clock input-only pin (stp) 0.0 - - ns t h(data) data hold time with respect to the rising edge of pin clock bidirectional pins (data[7:0]) as inputs [2] 0.0 - - ns t d(dir) dir output delay with respect to the rising edge of pin clock output-only pin dir - - 9.0 ns t d(nxt) nxt output delay with respect to the rising edge of pin clock output-only pin nxt - - 9.0 ns t d(data) data output delay with respect to the rising edge of pin clock bidirectional pins (data[3:0]) as output [2] - - 4.4 ns c l load capacitance pins data[3:0], clock, dir, nxt, stp [3] t d =4ns --10pf t d = 4.4 ns - - 15 pf
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 71 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver table 69. dynamic characteristics: analog i/o pins (dp, dm) in usb mode v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. typical values refer to v cc = 3.6 v; v cc(i/o) = 3.3 v; t amb = +25 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit high-speed driver characteristics; see figure 26 t hsr rise time (10 % to 90 %) drive 45 w to gnd on dp and dm 500 - - ps t hsf fall time (10 % to 90 %) drive 45 w to gnd on dp and dm 500 - - ps full-speed driver characteristics; see figure 26 t fr rise time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t ff fall time c l = 50 pf; 10 % to 90 % of | v oh - v ol | 4 - 20 ns t frfm differential rise and fall time matching t fr /t ff ; excluding the ?rst transition from the idle state 90 - 111.1 % low-speed driver characteristics; see figure 26 t lr transition time: rise time c l = 200 pf to 600 pf; 1.5 k w pull-up on dm enabled; 10 % to 90 % of | v oh - v ol | 75 - 300 ns t lf transition time: fall time c l = 200 pf to 600 pf; 1.5 k w pull-up on dm enabled; 10 % to 90 % of | v oh - v ol | 75 - 300 ns t lrfm rise and fall time matching t lr /t lf ; excluding the ?rst transition from the idle state 80 - 125 % table 70. dynamic characteristics: analog i/o pins (dp, dm) in transparent uart mode v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit full-speed driver characteristics (dm only) t r(uart) rise time for uart txd c l = 185 pf; 0.37 v to 2.16 v 25 - 75 ns t f(uart) fall time for uart txd c l = 185 pf; 2.16 v to 0.37 v 25 - 75 ns t plh(drv) driver propagation delay (low to high) c l = 185 pf; data0 to dm - - 39 ns t phl(drv) driver propagation delay (high to low) c l = 185 pf; data0 to dm - - 34 ns low-speed driver characteristics (dm only) t r(uart) rise time for uart txd c l = 185 pf; 0.37 v to 2.16 v 100 - 400 ns t f(uart) fall time for uart txd c l = 185 pf; 2.16 v to 0.37 v 100 - 400 ns t plh(drv) driver propagation delay (low to high) c l = 185 pf; data0 to dm - - 614 ns t phl(drv) driver propagation delay (high to low) c l = 185 pf; data0 to dm - - 614 ns full-speed receiver characteristics (dp only) t plh(rcv) receiver propagation delay (low to high) dp to data1 - - 7 ns t phl(rcv) receiver propagation delay (high to low) dp to data1 - - 7 ns low-speed receiver characteristics (dp only) t plh(rcv) receiver propagation delay (low to high) dp to data1 - - 7 ns t phl(rcv) receiver propagation delay (high to low) dp to data1 - - 7 ns
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 72 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver table 71. dynamic characteristics: analog i/o pins (dp, dm) in serial mode v cc = 3.0 v to 4.5 v; v cc(i/o) = 3.0 v to 3.6 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit driver timing (valid only for serial mode) t plh(drv) driver propagation delay (low to high) tx_dat, tx_se0 to dp, dm; see figure 27 - - 11 ns t phl(drv) driver propagation delay (high to low) tx_dat, tx_se0 to dp, dm; see figure 27 - - 11 ns t phz driver disable delay from high level tx_enable to dp, dm; see figure 28 - - 12 ns t plz driver disable delay from low level tx_enable to dp, dm; see figure 28 - - 12 ns t pzh driver enable delay to high level tx_enable to dp, dm; see figure 28 - - 20 ns t pzl driver enable delay to low level tx_enable to dp, dm; see figure 28 - - 20 ns receiver timing (valid only for serial mode) differential receiver t plh(rcv) receiver propagation delay (low to high) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 29 - - 17 ns t phl(rcv) receiver propagation delay (high to low) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 29 - - 17 ns single-ended receiver t plh(se) single-ended propagation delay (low to high) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 29 - - 17 ns t phl(se) single-ended propagation delay (high to low) dp, dm to rx_rcv, rx_dp and rx_dm; see figure 29 - - 17 ns fig 26. rise time and fall time fig 27. timing of tx_dat and tx_se0 to dp and dm fig 28. timing of tx_enable to dp and dm fig 29. timing of dp and dm to rx_rcv, rx_dp and rx_dm 004aaa861 v ol t hsr , t fr , t lr t hsf , t ff , t lf v oh 90 % 10 % 10 % 90 % 004aaa573 v ol v oh t phl(drv) t plh(drv) v crs v crs 0.9 v 0.9 v 1.8 v 0 v logic input differential data lines 004aaa574 v ol v oh t pzh t pzl t phz t plz v oh - 0.3 v v ol + 0.3 v v crs 0.9 v 0.9 v 1.8 v 0 v logic input differential data lines t plh(se) t phl(se) 001aai187 v ol v oh t phl(rcv) t plh(rcv) v crs v crs 0.9 v 0.9 v 2.0 v 0.8 v logic output differential data lines
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 73 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 16. application information fig 30. ulpi timing interface clock control in (stp) data in (8-bit) t su(stp) t h(stp) t su(data) t h(data) control out (dir, nxt) data out (8-bit) 004aaa722 t d(dir) , t d(nxt) t d(data) t d(dir) , t d(nxt) table 72. recommended bill of materials designator application part type remark c bypass highly recommended for all applications 0.1 m f 20 % - c ?lter highly recommended for all applications 4.7 m f 20 % use a low esr capacitor (0.2 w to 2 w ) for best performance c vbus mandatory for peripherals 1 m fto10 m f use low esr capacitor mandatory for host 120 m f (min) use low esr capacitor mandatory for otg 1 m fto6.5 m f use low esr capacitor c xtal in all applications 18 pf 20 % - d esd recommended to prevent damages from esd - ip4359cx4/lf; wafer-level chip-scale package (wlcsp); esd iec 61000-4-2 level 4; 15 kv contact; 15 kv air discharge compliant protection. note: isp1705 and ip4359cx4/lf together have an iec 61000-4-2 contact discharge tolerance of 20 kv. r rref mandatory in all applications 12 k w 1% - r s(vbus) recommended for peripherals or external 5 v applications 1k w 5% - r pullup recommended; for applications with an external v bus supply controlled by psw_n 10 k w - xtal mandatory in all applications 19.2 mhz c l = 10 pf; r s < 220 w ; c xtal =18pf 24 mhz c l = 10 pf; r s < 160 w ; c xtal =18pf
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 74 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver this ?gure shows the hvqfn pinout. for the tfbga ballout, see t ab le 3 . (1) connect to either gnd or v cc(i/o) , depending on the clock frequency used. see t ab le 6 . fig 31. isp1705 in peripheral-only application isp1705 data0 v cc(i/o) rref dm dp fault id v cc psw_n data1 data2 chip_sel data3 clock data4 data5 data6 data7 nxt 14 8 9 10 6 5 4 26 2 23 24 25 27 28 29 30 35 36 1 004aab061 v bus reg3v3 xtal2 17 12 13 stp dir reg1v8 v cc(i/o) 3 18 19 22 usb peripheral controller usb standard-b receptacle shield v bus d - d+ gnd 4 3 2 1 data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir v cc(i/o) chip_sel gnd ip4359cx4/lf b1 a1 a2 c bypass r rref c vbus c bypass c filter c bypass c filter r s(vbus) cfg1 (1) 31 cfg0 7 cfg2 (1) 32 21 v cc(i/o) v cc c bypass 15 n.c. 11 xtal1 16 b2 5 shield 6 c bypass d esd reset_n 20 c bypass c bypass v cc(i/o) 33 c xtal1 chip_sel_n 34
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 75 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver this ?gure shows the hvqfn pinout. for the tfbga ballout, see t ab le 3 . (1) connect to either gnd or v cc(i/o) , depending on the crystal frequency used. see t ab le 6 . fig 32. isp1705 in otg application isp1705 dm dp fault id psw_n 14 9 10 6 5 004aab062 v bus xtal2 17 13 reg1v8 18 usb micro-ab receptacle 5 4 3 2 1 +5 v in fault on out v bus switch r s(vbus) r rref ip4359cx4/lf b1 a1 a2 d esd c vbus c bypass c filter c bypass c filter cfg1 (1) 31 cfg2 (1) 32 data0 data1 data2 chip_sel data3 clock data4 data5 data6 data7 nxt stp dir data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir chip_sel cfg0 7 otg controller v cc(i/o) v cc 8 33 v cc(i/o) 3 v cc(i/o) c bypass 21 v cc(i/o) v cc c bypass gnd 15 n.c. 11 34 chip_sel_n r pullup 2 23 24 25 27 28 29 30 35 36 1 19 22 xtal1 16 b2 6 7 8 9 shield v bus d - d+ id gnd shield shield shield c xtal c xtal xtal c bypass 4 rref 26 v cc(i/o) reset_n 20 12 reg3v3 c bypass c bypass
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 76 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver this ?gure shows the hvqfn pinout. for the tfbga ballout, see t ab le 3 . (1) connect to either gnd or v cc(i/o) , depending on the crystal frequency used. see t ab le 6 . fig 33. isp1705 in host application isp1705 rref dm dp fault id psw_n 14 9 10 6 5 4 004aab063 v bus reg3v3 xtal1 xtal2 17 16 12 13 usb standard-a receptacle v bus d - d+ gnd 4 3 2 1 +5 v in fault on out v bus switch ip4359cx4/lf a2 d esd r rref r pullup c vbus c bypass c filter c xtal c xtal xtal cfg1 (1) 31 cfg2 (1) 32 reg1v8 18 c bypass c filter data0 data1 data2 chip_sel data3 clock data4 data5 data6 data7 nxt stp dir data0 data1 data2 data3 data4 data5 data6 data7 clock nxt stp dir chip_sel cfg0 usb host controller v cc(i/o) v cc 8 26 v cc(i/o) 3 v cc(i/o) c bypass 21 v cc(i/o) v cc c bypass gnd 15 chip_sel_n 34 11 n.c. a1 b1 b2 shield 5 shield 6 7 2 23 24 25 27 28 29 30 35 36 1 19 22 c bypass c bypass c bypass v cc(i/o) reset_n 33 20
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 77 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 17. package outline fig 34. package outline sot818-1 (hvqfn36) references outline version european projection issue date iec jedec jeita sot818-1 - - - mo-220 - - - sot818-1 03-06-13 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 1 0.05 0.00 0.30 0.18 5.1 4.9 3.75 3.45 5.1 4.9 3.75 3.45 3.2 3.2 0.1 a 1 dimensions (mm are the original dimensions) hvqfn36: plastic thermal enhanced very thin quad flat package; no leads; 36 terminals; body 5 x 5 x 0.85 mm 0 2.5 5 mm scale b c 0.2 d (1) d h e (1) e h e 0.4 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 terminal 1 index area d e b a b l a c c b v m w m e 1 e 2 terminal 1 index area e h d h e e 10 18 36 28 27 19 9 1 y y 1 c c x detail x a a 1 c
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 78 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver fig 35. package outline sot912-1 (tfbga36) references outline version european projection issue date iec jedec jeita sot912-1 sot912-1 05-08-09 05-09-01 unit a max mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 3.6 3.4 3.6 3.4 a 1 dimensions (mm are the original dimensions) tfbga36: plastic thin fine-pitch ball grid array package; 36 balls; body 3.5 x 3.5 x 0.8 mm 0 2.5 5 mm scale a 2 b d e e 2 2.5 e 0.5 e 1 2.5 y 1 0.1 v 0.15 w 0.05 y 0.08 - - - - - - - - - b e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m ball a1 index area a b c d e f 246 135 ball a1 index area b a e d c y c y 1 x detail x a 1 a 2 a
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 79 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 80 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 18.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 36 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 73 and 74 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 36 . table 73. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 74. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 81 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 19. abbreviations msl: moisture sensitivity level fig 36. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 75. abbreviations acronym description asic application speci?c integrated circuit atx analog usb transceiver cdm charged device model cd-dvd compact disc - digital video disc cd-rom compact disc - read-only memory cd-rw compact disc - rewritable ddr dual data rate emi electromagnetic interference eop end-of-packet esd electrostatic discharge esr effective series resistance fpga field programmable gate-array fs full speed hbm human body model hnp host negotiation protocol hs high speed id identi?cation iec international electrotechnical commission ls low speed
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 82 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 20. glossary a-device an otg device with an attached micro-a plug. b-device an otg device with an attached micro-b plug. link asic, soc or fpga that contains the usb host or peripheral core. phy physical layer containing the usb transceiver. 21. references [1] universal serial bus speci?cation rev. 2.0 [2] on-the-go supplement to the usb 2.0 speci?cation rev. 1.3 [3] utmi+ low pin interface (ulpi) speci?cation rev. 1.1 mm machine model nrzi non-return to zero inverted otg on-the-go pda personal digital assistant phy physical pid packet identi?er pll phase-locked loop por power-on reset rohs restriction of hazardous substances rxcmd receive command rxd receive data sdr single data rate se0 single-ended zero soc system-on-chip sof start-of-frame srp session request protocol sync synchronous ttl transistor-transistor logic txcmd transmit command txd transmit data uart universal asynchronous receiver-transmitter ulpi utmi+ low pin interface usb universal serial bus usb-if usb implementers forum utmi usb transceiver macrocell interface utmi+ usb transceiver macrocell interface plus wlcsp wafer-level chip-scale package table 75. abbreviations continued acronym description
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 83 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver [4] utmi+ speci?cation rev. 1.0 [5] usb 2.0 transceiver macrocell interface (utmi) speci?cation ver. 1.05 [6] electrostatic discharge (esd) sensitivity testing human body model (hbm) (jesd22-a114d) [7] electrostatic discharge (esd) sensitivity testing machine model (mm) (jesd22-a115-a) [8] field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components (jesd22-c101-c) [9] electromagnetic compatibility (emc) - part 4-2: testing and measurement techniques - electrostatic discharge immunity test (iec 61000-4-2) 22. revision history table 76. revision history document id release date data sheet status change notice supersedes isp1705_1 20080613 product data sheet - -
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 84 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 23. legal information 23.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 23.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 23.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 23.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 24. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 85 of 89 continued >> nxp semiconductors isp1705 ulpi hi-speed usb transceiver 25. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 2. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 4. recommended v bus capacitor value . . . . . . .18 table 5. otg_ctrl register power control bits . . . . . .19 table 6. allowed crystal or clock frequency on the xtal1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 7. external capacitor values for 13 mhz or 19.2 mhz clock frequency . . . . . . . . . . . . . . . .20 table 8. external capacitor values for 24 mhz or 26 mhz clock frequency . . . . . . . . . . . . . . . . .20 table 9. pin states in power-down mode . . . . . . . . . . .22 table 10. ulpi signal description . . . . . . . . . . . . . . . . . .23 table 11. signal mapping during low-power mode . . . . .24 table 12. signal mapping for 6-pin serial mode . . . . . . .25 table 13. signal mapping for 3-pin serial mode . . . . . . .26 table 14. uart signal mapping . . . . . . . . . . . . . . . . . . .26 table 15. operating states and their corresponding resistor settings . . . . . . . . . . . . . . . . . . . . . . . .29 table 16. txcmd byte format . . . . . . . . . . . . . . . . . . . . .31 table 17. rxcmd byte format . . . . . . . . . . . . . . . . . . . . .32 table 18. linestate[1:0] encoding for upstream facing ports: peripheral . . . . . . . . . . . . . . . . . .33 table 19. linestate[1:0] encoding for downstream facing ports: host . . . . . . . . . . . . . . . . . . . . . . .33 table 20. encoded v bus voltage state . . . . . . . . . . . . . .33 table 21. v bus indicators in rxcmd required for typical applications . . . . . . . . . . . . . . . . . . . . . .34 table 22. encoded usb event signals . . . . . . . . . . . . . .35 table 23. phy pipeline delays . . . . . . . . . . . . . . . . . . . . .39 table 24. link decision times . . . . . . . . . . . . . . . . . . . . .40 table 25. register map . . . . . . . . . . . . . . . . . . . . . . . . . .52 table 26. vendor_id_low - vendor id low register (address r = 00h) bit description . . . . . . . . . . .52 table 27. vendor_id_high - vendor id high register (address r = 01h) bit description . . . .52 table 28. product_id_low - product id low register (address r = 02h) bit description . . . .53 table 29. product_id_high - product id high register (address r = 03h) bit description . . . .53 table 30. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit allocation . . . . . . . . . . . . . . . . . . .53 table 31. func_ctrl - function control register (address r = 04h to 06h, w = 04h, s = 05h, c = 06h) bit description . . . . . . . . . . . . . . . . . .53 table 32. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit allocation . . . . . . . . . . . . . . . . . . . 55 table 33. intf_ctrl - interface control register (address r = 07h to 09h, w = 07h, s = 08h, c = 09h) bit description . . . . . . . . . . . . . . . . . . 55 table 34. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit allocation . . . . . . . . . . . . . . . . . . . 56 table 35. otg_ctrl - otg control register (address r = 0ah to 0ch, w = 0ah, s = 0bh, c = 0ch) bit description . . . . . . . . . . . . . . . . . 57 table 36. usb_intr_en_r - usb interrupt enable rising register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit allocation . . . 58 table 37. usb_intr_en_r - usb interrupt enable rising register (address r = 0dh to 0fh, w = 0dh, s = 0eh, c = 0fh) bit description . . 58 table 38. usb_intr_en_f - usb interrupt enable falling register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit allocation . . . . 58 table 39. usb_intr_en_f - usb interrupt enable falling register (address r = 10h to 12h, w = 10h, s = 11h, c = 12h) bit description . . . 59 table 40. usb_intr_stat - usb interrupt status register (address r = 13h) bit allocation . . . . . 59 table 41. usb_intr_stat - usb interrupt status register (address r = 13h) bit description . . . . 59 table 42. usb_intr_l - usb interrupt latch register (address r = 14h) bit allocation . . . . . 60 table 43. usb_intr_l - usb interrupt latch register (address r = 14h) bit description . . . . 60 table 44. debug - debug register (address r = 15h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 45. debug - debug register (address r = 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 46. scratch - scratch register (address r = 16h to 18h, w = 16h, s = 17h, c = 18h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 47. carkit_ctrl - carkit control register (address r = 19h to 1bh, w = 19h, s = 1ah, c = 1bh) bit allocation . . . . . . . . . . . . . . . . . . . 61 table 48. carkit_ctrl - carkit control register (address r = 19h to 1bh, w = 19h, s = 1ah, c = 1bh) bit description . . . . . . . . . . . . . . . . . . 61 table 49. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh, c = 3fh) bit allocation . . . . . . . . . . . . . . . . . . . 62 table 50. pwr_ctrl - power control register (address r = 3dh to 3fh, w = 3dh, s = 3eh,
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 86 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver c = 3fh) bit description . . . . . . . . . . . . . . . . . .62 table 51. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .63 table 52. recommended operating conditions . . . . . . . .63 table 53. static characteristics: supply pins . . . . . . . . . .64 table 54. static characteristics: digital pins . . . . . . . . . . .64 table 55. static characteristics: digital input pin fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 56. static characteristics: digital output pin psw_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 table 57. static characteristics: analog pins (dp, dm) . .65 table 58. static characteristics: analog pin v bus . . . . . .67 table 59. static characteristics: analog pin cfg0 . . . . . .68 table 60. static characteristics: id detection circuit . . . .68 table 61. static characteristics: resistor reference . . . . .68 table 62. static characteristics: regulator . . . . . . . . . . . .68 table 63. static characteristics: pin xtal1 . . . . . . . . . . .68 table 64. dynamic characteristics: reset and power . . . .69 table 65. dynamic characteristics: clock applied to xtal1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 table 66. dynamic characteristics: clock output . . . . .69 table 67. dynamic characteristics: digital i/o pins (sdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 68. dynamic characteristics: digital i/o pins (ddr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 table 69. dynamic characteristics: analog i/o pins (dp, dm) in usb mode . . . . . . . . . . . . . . . . . .71 table 70. dynamic characteristics: analog i/o pins (dp, dm) in transparent uart mode . . . . . . . .71 table 71. dynamic characteristics: analog i/o pins (dp, dm) in serial mode . . . . . . . . . . . . . . . . . .72 table 72. recommended bill of materials . . . . . . . . . . . .73 table 73. snpb eutectic process (from j-std-020c) . . .80 table 74. lead-free process (from j-std-020c) . . . . . .80 table 75. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .81 table 76. revision history . . . . . . . . . . . . . . . . . . . . . . . .83
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 87 of 89 nxp semiconductors isp1705 ulpi hi-speed usb transceiver 26. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin con?guration hvqfn36. . . . . . . . . . . . . . . . . .5 fig 3. pin con?guration tfbga36 . . . . . . . . . . . . . . . . . .5 fig 4. digital overcurrent detection scheme. . . . . . . . . .12 fig 5. internal power-on reset timing . . . . . . . . . . . . . . .13 fig 6. power-up and reset sequence required before the ulpi bus is ready for use. . . . . . . . . . . . . . . .14 fig 7. interface behavior with respect to reset_n. . . .15 fig 8. interface behavior with respect to chip select . . .16 fig 9. v bus pin internal pull-up and pull-down scheme .19 fig 10. interface behavior when entering uart mode . .28 fig 11. interface behavior when exiting uart mode . . . .28 fig 12. single and back-to-back rxcmds from the isp1705 to the link. . . . . . . . . . . . . . . . . . . . . . . .32 fig 13. rxcmd a_vbus_vld indicator source . . . . . . .34 fig 14. example of register write, register read, extended register write and extended register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 fig 15. usb reset and high-speed detection handshake (chirp) sequence . . . . . . . . . . . . . . . .38 fig 16. example of using the isp1705 to transmit and receive usb data . . . . . . . . . . . . . . . . . . . . . . . . .39 fig 17. high-speed transmit-to-transmit packet timing. . .40 fig 18. high-speed receive-to-transmit packet timing . . .41 fig 19. preamble sequence . . . . . . . . . . . . . . . . . . . . . . .42 fig 20. full speed suspend and resume . . . . . . . . . . . . .43 fig 21. high speed suspend and resume . . . . . . . . . . . .45 fig 22. remote wake-up from low-power mode . . . . . . .47 fig 23. transmitting usb packets without automatic sync and eop generation . . . . . . . . . . . . . . . . .48 fig 24. example of transmit followed by receive in 6-pin serial mode . . . . . . . . . . . . . . . . . . . . . . .50 fig 25. example of transmit followed by receive in 3-pin serial mode . . . . . . . . . . . . . . . . . . . . . . .50 fig 26. rise time and fall time . . . . . . . . . . . . . . . . . . . . .72 fig 27. timing of tx_dat and tx_se0 to dp and dm . .72 fig 28. timing of tx_enable to dp and dm. . . . . . . . .72 fig 29. timing of dp and dm to rx_rcv, rx_dp and rx_dm . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 fig 30. ulpi timing interface . . . . . . . . . . . . . . . . . . . . . .73 fig 31. isp1705 in peripheral-only application . . . . . . . .74 fig 32. isp1705 in otg application . . . . . . . . . . . . . . . .75 fig 33. isp1705 in host application . . . . . . . . . . . . . . . . .76 fig 34. package outline sot818-1 (hvqfn36) . . . . . . .77 fig 35. package outline sot912-1 (tfbga36). . . . . . . .78 fig 36. temperature pro?les for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
isp1705_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 june 2008 88 of 89 continued >> nxp semiconductors isp1705 ulpi hi-speed usb transceiver 27. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 9 8.1 ulpi interface controller . . . . . . . . . . . . . . . . . . 9 8.2 usb serializer and deserializer. . . . . . . . . . . . . 9 8.3 hi-speed usb (usb 2.0) atx . . . . . . . . . . . . . 9 8.4 voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 10 8.5 crystal oscillator and pll. . . . . . . . . . . . . . . . 10 8.6 uart buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.7 otg module . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.7.1 id detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.7.2 v bus comparators. . . . . . . . . . . . . . . . . . . . . . 11 8.7.2.1 v bus valid comparator . . . . . . . . . . . . . . . . . . 11 8.7.2.2 session valid comparator . . . . . . . . . . . . . . . . 11 8.7.2.3 session end comparator. . . . . . . . . . . . . . . . . 11 8.7.3 srp charge and discharge resistors . . . . . . . 12 8.8 port power control. . . . . . . . . . . . . . . . . . . . . . 12 8.9 band gap reference voltage . . . . . . . . . . . . . . 12 8.10 power-on reset (por) . . . . . . . . . . . . . . . . . 12 8.11 power-up, reset and bus idle sequence . . . . . 13 8.11.1 interface protection . . . . . . . . . . . . . . . . . . . . . 15 8.11.2 interface behavior with respect to reset_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.11.3 interface behavior with respect to chip select. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.12 detailed description of pins . . . . . . . . . . . . . . 16 8.12.1 data[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.2 v cc(i/o) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.12.3 rref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.4 dp and dm . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.5 cfg0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.6 v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.7 id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.8 fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.12.9 reg3v3 and reg1v8 . . . . . . . . . . . . . . . . . . 18 8.12.10 v bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.12.11 psw_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.12.12 xtal1 and xtal2. . . . . . . . . . . . . . . . . . . . . . 19 8.12.13 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.12.14 reset_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.12.15 stp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.12.16 nxt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.12.17 clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.12.18 cfg1, cfg2 . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.12.19 chip_sel, chip_sel_n . . . . . . . . . . . . . . . 21 8.12.20 gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 modes of operation . . . . . . . . . . . . . . . . . . . . . 22 9.1 power modes . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.1.2 power-down mode . . . . . . . . . . . . . . . . . . . . . 22 9.2 ulpi modes . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.1 synchronous mode . . . . . . . . . . . . . . . . . . . . 23 9.2.2 low-power mode . . . . . . . . . . . . . . . . . . . . . . 24 9.2.3 6-pin full-speed or low-speed serial mode . . . 25 9.2.4 3-pin full-speed or low-speed serial mode . . . 25 9.2.5 transparent uart mode . . . . . . . . . . . . . . . . 26 9.3 usb state transitions . . . . . . . . . . . . . . . . . . . 29 10 protocol description . . . . . . . . . . . . . . . . . . . . 31 10.1 ulpi references . . . . . . . . . . . . . . . . . . . . . . . 31 10.2 txcmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.3 rxcmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.3.1 linestate encoding . . . . . . . . . . . . . . . . . . . . . 32 10.3.2 v bus state encoding . . . . . . . . . . . . . . . . . . . . 33 10.3.3 using and selecting the v bus state encoding. 34 10.3.3.1 standard usb host controllers. . . . . . . . . . . . 34 10.3.3.2 standard usb peripheral controllers . . . . . . . 35 10.3.3.3 otg devices . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.3.4 rxevent encoding . . . . . . . . . . . . . . . . . . . . . 35 10.3.4.1 rxactive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.3.4.2 rxerror. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3.4.3 hostdisconnect . . . . . . . . . . . . . . . . . . . . . . . 36 10.4 register read and write operations . . . . . . . . 36 10.5 usb reset and high-speed detection handshake (chirp) . . . . . . . . . . . . . . . . . . . . . 36 10.6 usb packet transmit and receive . . . . . . . . . . 39 10.6.1 usb packet timing . . . . . . . . . . . . . . . . . . . . . 39 10.6.1.1 isp1705 pipeline delays. . . . . . . . . . . . . . . . . 39 10.6.1.2 allowed link decision time . . . . . . . . . . . . . . . 39 10.7 preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.8 usb suspend and resume . . . . . . . . . . . . . . . 42 10.8.1 full-speed or low-speed host-initiated suspend and resume . . . . . . . . . . . . . . . . . . . 42 10.8.2 high speed suspend and resume . . . . . . . . . 43 10.8.3 remote wake-up . . . . . . . . . . . . . . . . . . . . . . 46 10.9 no automatic sync and eop generation (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.10 on-the-go operations . . . . . . . . . . . . . . . . . . 48
nxp semiconductors isp1705 ulpi hi-speed usb transceiver ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 13 june 2008 document identifier: isp1705_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 10.10.1 otg comparators . . . . . . . . . . . . . . . . . . . . . . 49 10.10.2 pull-up and pull-down resistors. . . . . . . . . . . . 49 10.10.3 id detection. . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.10.4 v bus charge and discharge resistors . . . . . . . 49 10.11 serial modes. . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.12 aborting transfers . . . . . . . . . . . . . . . . . . . . . . 51 10.13 avoiding contention on the ulpi data bus . . . 51 11 register map . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 vendor_id_low register . . . . . . . . . . . . . . 52 11.2 vendor_id_high register. . . . . . . . . . . . . . 52 11.3 product_id_low register . . . . . . . . . . . . . 53 11.4 product_id_high register . . . . . . . . . . . . 53 11.5 func_ctrl register . . . . . . . . . . . . . . . . . . . 53 11.6 intf_ctrl register . . . . . . . . . . . . . . . . . . . . 55 11.7 otg_ctrl register . . . . . . . . . . . . . . . . . . . . 56 11.8 usb_intr_en_r register . . . . . . . . . . . . . . . 58 11.9 usb_intr_en_f register . . . . . . . . . . . . . . . 58 11.10 usb_intr_stat register. . . . . . . . . . . . . . . . 59 11.11 usb_intr_l register . . . . . . . . . . . . . . . . . . . 59 11.12 debug register . . . . . . . . . . . . . . . . . . . . . . . 60 11.13 scratch register . . . . . . . . . . . . . . . . . . . . . 61 11.14 carkit_ctrl register . . . . . . . . . . . . . . . . . 61 11.15 pwr_ctrl register . . . . . . . . . . . . . . . . . . . . 62 12 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 63 13 recommended operating conditions. . . . . . . 63 14 static characteristics. . . . . . . . . . . . . . . . . . . . 64 15 dynamic characteristics . . . . . . . . . . . . . . . . . 69 16 application information. . . . . . . . . . . . . . . . . . 73 17 package outline . . . . . . . . . . . . . . . . . . . . . . . . 77 18 soldering of smd packages . . . . . . . . . . . . . . 79 18.1 introduction to soldering . . . . . . . . . . . . . . . . . 79 18.2 wave and re?ow soldering . . . . . . . . . . . . . . . 79 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 79 18.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 80 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 81 20 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 21 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 22 revision history . . . . . . . . . . . . . . . . . . . . . . . . 83 23 legal information. . . . . . . . . . . . . . . . . . . . . . . 84 23.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 84 23.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 23.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 23.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 24 contact information. . . . . . . . . . . . . . . . . . . . . 84 25 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 26 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 27 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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